ARTERIS, INC.

A computer-implemented design method includes creating a first elaborated design of an electronic system having a set of valid mode combinations, creating a second elaborated design of the system, creating a first system map from the first elaborated design, and creating a second system map from the second design. The method is implemented using a design tool. In some embodiments, the design tool includes a trained machine learning model. The first system map includes an address map for each valid mode combination of interest, and the second system map includes an address map for each valid mode combination of interest. If the first and second system maps are not equivalent, the second elaborated design is corrected prior to running a simulation on the second elaborated design.

System and methods are disclosed that are implemented by a tool for generation and synthesis of networks, such as a network-on-chip (NoC). The tool receives input from the user, either as a data file or through input in a graphical user interface (display). The tool generates a NoC from a set of physical constraints and performance constraints. The tool produces the NoC with all its elements, which is a legal and meets the constraints. The tool also receives as an input performance scenarios or performance requirement that can be used to transform an existing topology to satisfy the newly added requirements. The resulting output represents the network, such as the NoC, that meets the requirements.

A computer-implemented method includes accessing a network-on-chip (NoC) design in which a plurality of switches connect initiators to targets. The plurality of switches includes at least one merger-type switch having an arbiter and a plurality of inputs. For each merger-type switch, the number of initiators on the plurality of inputs is identified. Then a baseline number of initiators per input connection is determined. For each merger-type switch, if the number of initiators on an input exceeds the baseline number of initiators, and if access times on that input are unbalanced, then that input is split into a plurality of segments so that each of the segments carries the baseline number of initiators. The method ensures arbitration fairness without changing deadlock freedom of the NoC design.

An electronic system includes a plurality of logical processors, an interconnect, shared memory accessible by the logical processors via the interconnect, and a system directory. The system directory includes one or more tagged monitors at a first tier and a basic monitor at a second tier. The tagged monitors are configured to maintain exclusive cache coherence over a first set of addresses in the shared memory. The basic monitor is configured to maintain exclusive cache coherence over addresses in the shared memory that are not monitored by the tagged monitors.

A tool makes modifications to the chip floorplan and the network-on-chip (NoC) elements' position on the floorplan and updates the number and position of the pipeline elements in a pipeline stage automatically, resulting in fewer errors and higher productivity.

A computer-implemented method of generating a network-on-chip (NoC) topology for an electronic system includes creating a logical description of a plurality of empty sub-networks that connect initiators to targets of an electronic system. The method further includes placing the sub-networks within free space of a floorplan of the electronic system in a desired topology shape; and performing automated topology synthesis to add switches to each of the sub-networks such that the initiators are connected to the targets in accordance with a communication policy.

A computer-implemented method for designing a network-on-chip (NoC) includes accessing a NoC topology of an electronic system including initiators and targets. The NoC topology includes a plurality of NoC elements and channels that connect the initiators to the targets. The method further includes playing multiple scenarios, wherein each of the scenarios includes parallel source-to-destination transmissions of packets in the NoC topology; for each of the scenarios, detecting transmission issues along at least one of the channels that is shared; and performing buffer insertion in the NoC topology to address the transmission issues. The transmission issues involve clock rates of sources, destinations and the channels in the NoC topology.

An electronic system includes an interconnect for a plurality of cores. A directory-based cache coherence method for the electronic system includes receiving a request transaction including a plurality of writes; sending a request for ownership of a window of cache lines corresponding to the writes; granting ownership to the cache lines without regard for order; and committing the write that is oldest once ownership has been granted to its corresponding cache line.

In a multi-core electronic system, a directory-based method of processing a request transaction includes, upon receipt of the request transaction, communicating with a plurality of directories to acquire ownership of cache lines to establish a single point of serialization. Write data is thereafter streamed to owned cache lines in at least two targets in parallel while keeping ordered write observation. The writes to the at least two targets are processed out of order but observed in order.

A computer-implemented method for electronic computer-aided design of an electronic system includes collecting a plurality of input files from a corresponding plurality of multiple sources in different formats. The input files describe a hardware/software interface in an electronic system. The method further includes building an internal model of hardware/software behavior combinations of the hardware/software interface, including mapping data in the input files to the internal model; and verifying that the internal model is self-consistent and correct.