ARTERIS, INC.

A computer-implemented design method includes creating a first elaborated design of an electronic system having a set of valid mode combinations, creating a second elaborated design of the system, creating a first system map from the first elaborated design, and creating a second system map from the second design. The method is implemented using a design tool. In some embodiments, the design tool includes a trained machine learning model. The first system map includes an address map for each valid mode combination of interest, and the second system map includes an address map for each valid mode combination of interest. If the first and second system maps are not equivalent, the second elaborated design is corrected prior to running a simulation on the second elaborated design.

System and methods are disclosed that are implemented by a tool for generation and synthesis of networks, such as a network-on-chip (NoC). The tool receives input from the user, either as a data file or through input in a graphical user interface (display). The tool generates a NoC from a set of physical constraints and performance constraints. The tool produces the NoC with all its elements, which is a legal and meets the constraints. The tool also receives as an input performance scenarios or performance requirement that can be used to transform an existing topology to satisfy the newly added requirements. The resulting output represents the network, such as the NoC, that meets the requirements.

A computer-implemented method includes accessing a network-on-chip (NoC) design in which a plurality of switches connect initiators to targets. The plurality of switches includes at least one merger-type switch having an arbiter and a plurality of inputs. For each merger-type switch, the number of initiators on the plurality of inputs is identified. Then a baseline number of initiators per input connection is determined. For each merger-type switch, if the number of initiators on an input exceeds the baseline number of initiators, and if access times on that input are unbalanced, then that input is split into a plurality of segments so that each of the segments carries the baseline number of initiators. The method ensures arbitration fairness without changing deadlock freedom of the NoC design.

A computer-implemented method of generating a network-on-chip (NoC) topology for an electronic system includes creating a logical description of a plurality of empty sub-networks that connect initiators to targets of an electronic system. The method further includes placing the sub-networks within free space of a floorplan of the electronic system in a desired topology shape; and performing automated topology synthesis to add switches to each of the sub-networks such that the initiators are connected to the targets in accordance with a communication policy.

A computer-implemented method for designing a network-on-chip (NoC) includes accessing a NoC topology of an electronic system including initiators and targets. The NoC topology includes a plurality of NoC elements and channels that connect the initiators to the targets. The method further includes playing multiple scenarios, wherein each of the scenarios includes parallel source-to-destination transmissions of packets in the NoC topology; for each of the scenarios, detecting transmission issues along at least one of the channels that is shared; and performing buffer insertion in the NoC topology to address the transmission issues. The transmission issues involve clock rates of sources, destinations and the channels in the NoC topology.

A computer-implemented method for electronic computer-aided design of an electronic system includes collecting a plurality of input files from a corresponding plurality of multiple sources in different formats. The input files describe a hardware/software interface in an electronic system. The method further includes building an internal model of hardware/software behavior combinations of the hardware/software interface, including mapping data in the input files to the internal model; and verifying that the internal model is self-consistent and correct.

A design tool is disclosed for using determination and generation of port connection of a network-on-chip (NoC), wherein the connections are presented in regular expression to allow for increase in speed of connection and reducing the potential for user introduced errors. The design tool allows for use of regular expressions to automate the process and autogenerating of names by the design tool using numbering in regular expression as a suffix. The design tool includes a large language model or a machine learning model that is trained for synthesis and generation of the NoC and is capable of providing suggested connections based on intake of regular expressions. The model can also receive feedback from past or previous synthesis for further training of the model.

A design tool is disclosed for using determination and generation of port connection of a network-on-chip (NoC), wherein the connections are presented in regular expression to allow for increase in speed of connection and reducing the potential for user introduced errors. The design tool allows for use of regular expressions to automate the process and autogenerating of names by the design tool using numbering in regular expression as a suffix. The design tool includes a large language model or a machine learning model that is trained for synthesis and generation of the NoC and is capable of providing suggested connections based on intake of regular expressions. The model can also receive feedback from past or previous synthesis for further training of the model.

A design tool is disclosed for receiving constraints and parameters for an architecture to be synthesized for a network-on-chip (NoC) The design tool partitions the architecture into new a number of project elements (e.g. an architecture). The design tool removes these partitions of architectures from the current master file representation of the whole project architecture and saves the partitioned portions to the new sub-projects. The design tool copies any dependencies detected (e.g. if there is an external protocol defined and the architecture uses it) into the new sub-projects, such that each new sub-project is self-contained.

A design tool is disclosed for generation and synthesis of the network, such as a network-on-chip (NoC). The design tool starts with a deadlock free network design and makes changes or transforms the design to generate a desired NoC, including addressing paths that cross clock domain boundaries or have timing violations. The design tool considers intermediate and proximal regions during the insertion process of distance links, which eliminates distance violations resulting from clock and timing domain traversal by a path.