Company patents
ARTERIS, INC.
ARTERIS, INC. demonstrates a focused patent strategy, with nearly half of its portfolio (46.0%) in Electronic Design Automation (CAD/EDA) and a significant 31.9% in Computer Hardware Architecture, both showing consistent, albeit modest, growth in 2025 and so far in 2026. While Routing, Switching & QoS experienced a dramatic 350.0% growth in 2025, its sharp decline of 88.9% so far in 2026 suggests a highly volatile or shifting priority in this area, contrasting with the more stable core computing categories.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
113 US filings (since 2023) · 10 categories · 13 themes
Automated methods and tools for generating, optimizing, and verifying the physical layout and interconnections of electronic components, including integrated circuits, printed circuit boards, and system-level interface protection.
Enhancements to the physical and data link layers of network communication, focusing on hardware components, signal integrity, power efficiency, and efficient data transfer mechanisms for specific interfaces and buses.
Utilizing specialized hardware components such as network processing units (NPUs) or dedicated acceleration circuits to offload and speed up network packet processing, traffic generation, or time-sensitive network operations.
Systems and methods for automatically deploying, configuring, and updating network devices and services, including software updates, client onboarding, and topology management across various network types.
Techniques and systems designed to monitor network health, diagnose issues, optimize traffic flow, and ensure continuous operation and reduced downtime in complex network environments, including cloud and storage area networks.
Using computational design and simulation to optimize the performance characteristics of specific components or materials within a larger engineering system.
Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.
Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.
Novel hardware designs and processing pipelines tailored for specific computational tasks, such as graphics rendering, neural network operations, or matrix transformations, often involving custom circuits, memory arrays, or data flow mechanisms.
Techniques and systems for optimizing network traffic flow, distributing loads across multiple paths or resources, and ensuring quality of service based on various criteria like application type, latency, or resource availability. This includes dynamic path selection, congestion control, and resource allocation.
Computational methods for modeling and simulating photolithography processes, including mask design, aerial image generation, and defect prediction for semiconductor manufacturing.
Managing and optimizing network resources and services deployed at the edge of the network or within cloud environments, including distributed domain name resolution, resource exposure analysis, and traffic management specific to distributed architectures.
Systems and methods for automating multi-step tasks, business processes, or service interactions, often involving AI agents, programmable interfaces, or formal orchestration languages to streamline operations.
Patents
Showing 21-30 of 33
Physical Layer & Interface Optimization