Beijing ESWIN Computing Technology Co., Ltd.

An interface conversion circuit, a method for processing signals, and a device are provided. The interface conversion circuit interface includes: a storage unit, configured to write a first image signal output by a multimedia module interface according to a write address signal, read the first image signal according to a read address signal, and output the first image signal; a mapping unit, configured to reorder pixel components of the received first image signal to obtain a second image signal meeting the display requirement of a display module interface, and transmitting the second image signal to the display module interface; and a deviation detection unit, configured to acquire the write address signal and the read address signal and adjust a read timing and a write timing of the storage unit according to the write address signal and the read address signal.

The present application provides a processing apparatus. The processing apparatus includes a processing unit and a multi-stage pipelining. The processing unit is configured to execute instructions of the multi-stage pipelining; a first-stage pipelining in the multi-stage pipelining is configured to acquire a first instruction and transmit the first instruction and a first operand to the processing unit in response to acquiring the first operand of the first instruction, and the first-stage pipelining is any one stage of pipelining in the multi-stage pipelining; and the processing unit is configured to acquire a first processing result by receiving and processing the first instruction and the first operand.

The present application provides a method for processing an instruction, which processes an instruction based on an address stack. The address stack includes a first sub-stack and a second sub-stack, a target address of the first sub-stack is acquired based on a prediction result of an instruction, and a target address of the second sub-stack is acquired based on a committing result of an instruction. The method includes acquiring a prediction result of an operation instruction, wherein the prediction result indicates a predicted next instruction executed after the operation instruction; determining a processing operation for the first sub-stack according to the prediction result; and performing, according to a write pointer of the first sub-stack, the processing operation on the target address corresponding to the prediction result in the first sub-stack, wherein the write pointer of the first sub-stack restricts retreating in a process of performing the processing operation.

The disclosure provides a mobile industry processor interface (MIPI) circuit, a chip and an electronic device. The MIPI interface circuit includes N pins, a path control component, and N interface components. The mode of data transmission in the MIPI is controlled via the path control component, which improves the efficiency and flexibility of data transmission. Moreover, by multiplexing the interface components in the data paths of a display physical layer (DPHY) and a camera physical layer (CPHY), the complexity and cost of the MIPI interface circuit can be reduced, and the scope of application of the MIPI can be expanded.

An instruction flagging circuit includes: a first instruction detection sub-circuit for performing instruction detection on to-be-processed instructions to obtain a first detection result, wherein the first detection result includes a first conditional branch instruction and at least one non-jump instruction of the to-be-processed instructions, a jump range of the first conditional branch instruction is within a first range, and the non-jump instruction is to be executed when the first conditional branch instruction does not jump; and a first instruction flagging sub-circuit for setting, according to the first detection result, instruction flags for the first conditional branch instruction and the non-jump instruction to obtain target flagged instructions. The target flagged instructions indicate an instruction execution circuit to execute the non-jump instruction including the instruction flag when it is determined that the first conditional branch instruction jumps.

The present application provides a processor and a method for memory access instruction, and an electronic device, and relates to the field of computer technology. The method includes: the memory access unit generates the target physical memory address corresponding to the memory access instruction in case of receiving the memory access instruction, and transmits the target physical memory address to the cache unit and the programmable physical memory property detection unit respectively in the current clock cycle; the programmable physical memory property detection unit determines the detection result for the cache property of the target physical memory address in the current clock cycle; the cache unit performs the memory access operation at the target physical memory address based on the detection result for the cache property in the next clock cycle subsequent to the current clock cycle. This may reduce the logical depth of the critical memory access paths and improve the clock speed of the processor.

The present application provides a mutual exclusion (mutex) device, a mutually exclusive access method and system for a shared resource, and a host. The method is performed by a target host, where the target host is any host among multiple hosts, and the multiple hosts are connected to the mutex device and the shared resource through a bus. The mutex device includes a mutex status register and a mutex set register; the mutex set register includes multiple first fields, the multiple first fields are in one-to-one correspondence with the multiple hosts, and each first field is used for identifying a request status of the multiple hosts for a mutex. The mutex status register includes multiple second fields, the multiple second fields are in one-to-one correspondence with the multiple hosts and each second field is used for identifying a hold status of the multiple hosts for the mutex. The method includes: setting a first field corresponding to the target host in the mutex set register to a first value in case of a determination that the target host has transmitted a mutex request; and setting a second field corresponding to the target host in the mutex status register to a second value and accessing the shared resource in case of a determination that the target host has successfully requested the mutex. In the method, by means of the register group in the mutex device, multiple hosts are identified by the mutex set register and the mutex status register respectively and the shared resource may be simply and effectively accessed without relying on strong algorithms and at low costs, which has strong universality

An automatic gain control system and a control method, a power detector and a radio frequency receiver are provided, wherein the power detector includes: a detection circuit, having a first and second input terminals connected to respective first and second differential output terminals of the trans-impedance amplifier, and configured to sample a peak of a differential output signal of the trans-impedance amplifier along with a clock cycle and provide a differential detection signal at a first output node; a filter circuit converts energy of the differential detection signal obtained at the first output node into an output voltage, so that the power detector may be used to detect an output power of the trans-impedance amplifier and adjust, by a control logic unit, a gain or an output power of a low noise amplifier connected to a radio frequency signal.

A method and device for data processing, and a storage medium are provided. The device includes: a pre-decoding circuit configured to: determine a first sub-block of an instruction block stored in an ICache based on a fetch instruction, determine first pre-decoding information of the first sub-block based on position information of the first sub-block; a pre-decoding check circuit configured to: acquire second pre-decoding information of the first sub-block from the ICache, determine a check result corresponding to the first sub-block based on the first pre-decoding information and the second pre-decoding information, when the check result is a first check result, transmit the first check result to a pre-decoding repair circuit; and the pre-decoding repair circuit configured to: repair second pre-decoding information of at least one target sub-block in the instruction block based on the first pre-decoding information, write the repaired second pre-decoding information back into the ICache.

A processing apparatus and a system for executing data processing on a plurality of pieces of channel information are disclosed. The processing apparatus includes: a channel information acquiring circuit, configured to acquire target channel information among the plurality of pieces of channel information; a storing circuit, including a plurality of storage regions corresponding to the plurality of pieces of channel information; a reading circuit, configured to sequentially pre-store the data information from the plurality of storage regions of the storing circuit to the pre-storing circuit; and a pre-storing circuit, configured to pre-store the data information from the plurality of storage regions of the storing circuit to wait for use in the data processing, and output pre-stored target data information corresponding to the target channel information, according to the acquired target channel information, for use in the data processing.