BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Embodiments provide a semiconductor structure and a fabrication method thereof, which relate to the field of semiconductor technology. The method for fabricating a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array in the substrate; and forming a gate arranged around each of the active pillars, where a projection of the gate on the active pillar covers a channel region of the active pillar. Along a direction perpendicular to the substrate, the gate includes a first conductive layer and a second conductive layer sequentially arranged in a stack, and a work function of the first conductive layer is different from a work function of the second conductive layer.

A method for forming a semiconductor device includes the following operations. A stacked structure is provided, which includes a substrate, and sacrificial layers and semiconductor layers alternately stacked on surface of the substrate. Multiple first grooves and semiconductor pillars extending in first direction are included in the sacrificial layers and the semiconductor layers. Word line pillars are formed in second direction, intersect with the semiconductor pillars and surround the semiconductor pillars. Sources and drains are formed respectively on either side of the semiconductor pillars surrounded by the word line pillars by an epitaxial growth process. Bit lines are formed on a side of the sources or the drains, are connected with same, and extend in third direction. The first, second and third directions are pairwise perpendicular. Capacitors are formed on a side of the sources or the drains where the bit lines are not formed to form a semiconductor device.

The present disclosure relates to a thin film transistor and a method of manufacturing a thin film transistor. The thin film transistor includes: a substrate; an insulation layer on an upper surface of the substrate; a fin gate on an upper surface of the insulation layer; a surrounding gate dielectric layer and a surrounding channel, where the surrounding gate dielectric layer covers a top surface of the fin gate and a side surface of the fin gate, and the surrounding channel surrounds an outer wall of the surrounding gate dielectric layer; and a source region and a drain region on the upper surface of the substrate, where the source region and the drain region are located on two opposite sides of the fin gate respectively and are in contact with the surrounding channel.

The present disclosure provides a capacitor and a manufacturing method thereof, and a semiconductor device. The capacitor includes a plurality of bottom electrodes, a top electrode structure, a dielectric layer, and a gap filling layer, where the top electrode structure is formed on one side of each of the plurality of bottom electrodes, one side of the dielectric layer is in contact with the plurality of bottom electrodes and the other side is in contact with the top electrode structure, and the gap filling layer fills remaining gaps between the plurality of bottom electrodes.

A method for manufacturing a semiconductor device includes the following operations. A substrate is provided. Bit lines extending in a first direction are formed on the substrate. A first dielectric layer is formed on the bit lines. The first dielectric layer is etched from top to bottom to form channel holes in the first dielectric layer, in which the channel holes expose the bit lines. A channel layer is formed in each channel hole, in which the channel layer includes a first source/drain area, a channel area and a second source/drain area which are arranged from bottom to top, the first source/drain area is electrically connected to a respective one bit line. Word lines extending in a second direction are formed in the first dielectric layer.

A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.

A semiconductor device and a method for manufacturing the same. A substrate is provided. A first source-drain layer, a channel layer, and a second source-drain layer are sequentially stacked on the substrate. Both a gate dielectric layer and a gate structure surround the channel layer laterally. The gate structure includes a first portion extending laterally and a second portion extending upward from a periphery of the first portion. A second portion is located at a periphery of the second source-drain layer. A spacer layer is formed at an outer sidewall of the gate structure. The gate structure is etched to reduce a thickness of the gate structure. A sacrificial structure covering the gate structure is formed, and a capping layer covering the second source-drain layer, the sacrificial structure, and the spacer layer is formed. Thereby, the sacrificial structure is located at the periphery of the second source-drain layer and enclosed by the spacer layer. The capping layer is etched to obtain a first contact hole reaching the sacrificial structure. The sacrificial structure at the bottom of the first contact hole is removed to form a gap under the first contact hole. A first contact structure is formed in the first contact hole and the gap. Self-alignment between a bottom of the first contact structure and the gate structure is achieved, and the device has higher reliability.

Embodiments provide a semiconductor structure and a fabrication method thereof, which relate to the field of semiconductor technology. The method for fabricating a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array in the substrate; and forming a gate arranged around each of the active pillars, where a projection of the gate on the active pillar covers a channel region of the active pillar. Along a direction perpendicular to the substrate, the gate includes a first conductive layer and a second conductive layer sequentially arranged in a stack, and a work function of the first conductive layer is different from a work function of the second conductive layer.

A method for manufacturing a semiconductor device includes the following operations. A substrate is provided. Bit lines extending in a first direction are formed on the substrate. A first dielectric layer is formed on the bit lines. The first dielectric layer is etched from top to bottom to form channel holes in the first dielectric layer, in which the channel holes expose the bit lines. A channel layer is formed in each channel hole, in which the channel layer includes a first source/drain area, a channel area and a second source/drain area which are arranged from bottom to top, the first source/drain area is electrically connected to a respective one bit line. Word lines extending in a second direction are formed in the first dielectric layer.

A method for forming a capacitor includes: providing a substrate; sequentially forming a first sacrificial layer and a first support layer for covering the substrate; forming first openings penetrating through the first support layer; sequentially forming a second sacrificial layer and a second support layer for covering a remaining portion of the first support layer; forming through holes which sequentially penetrate through the second support layer, the second sacrificial layer, the remaining portion of the first support layer, and the first sacrificial layer; forming first electrode layers, each first electrode layer covering an inner wall of a respective one of the through holes; forming second openings penetrating through a remaining portion of the second support layer; and sequentially forming a dielectric layer and a second electrode layer for covering the first electrode layers, to form the capacitor.