BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

A semiconductor device, a manufacturing method therefor, and an electronic apparatus are disclosed. The semiconductor device includes: multiple transistors, distributed in different layers and stacked along a direction perpendicular to a substrate; a word line, penetrating the different layers and extending in the direction perpendicular to the substrate; the transistor includes a first electrode and a semiconductor layer surrounding a sidewall of the word line; the semiconductor layer includes a first groove with an opening facing away from the word line, the first electrode is within the first groove and connected to the semiconductor layer.

A semiconductor device, a manufacturing method therefor, and an electronic apparatus are disclosed. The semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate; a word line, penetrating the different layers and extending in the direction perpendicular to the substrate; the transistor includes a first electrode, a gate insulating layer, a semiconductor layer surrounding side walls of the word line, and a protective layer disposed between the semiconductor layer and side walls of the gate insulating layer; the first electrode is provided in a first groove of the semiconductor layer.

Provided are a transistor, a 3D stacked semiconductor device, a manufacturing method thereof, and an electronic device. The transistor includes a first electrode and a second electrode arranged on a substrate, a semiconductor layer arranged between the first electrode and the second electrode, and a gate electrode insulated from the semiconductor layer; the first electrode and the second electrode are separated in a first direction parallel to the substrate; the gate electrode extends along a second direction parallel to the substrate, the gate electrode includes a sidewall extending along the second direction and two end surfaces, one end surface is configured to be connected with a word line; at least a portion of the sidewall of the gate electrode is surrounded by a semiconductor layer; the first direction intersects with the second direction.

Provided is a memory cell. A vertical transistor of the memory cell includes a semiconductor pillar including a drain region, a channel region, and a source region disposed sequentially; and a gate insulating layer and a gate, the gate and at least a portion of the gate insulating layer being disposed sequentially around the channel region of the semiconductor pillar; wherein the vertical transistor includes at least one of: the gate insulating layer proximal to the source region having a greater dielectric constant than the gate insulating layer proximal to the drain region, or, the gate proximal to the source region having a greater work function than the gate proximal to the drain region; and the drain region is configured to be electrically connected to a bitline, and the source region is configured to be electrically connected to a capacitor structure.

Disclosed is a method for implementing a universal content-addressable memory based on N-type and P-type ferroelectric field-effect transistors, relating to the field of novel storage and computing technology. According to the method, by utilizing the complementary characteristics of N-type FeFET and P-type FeFET, all of TCAM, MACM, and ACAM may be implemented without additional hardware overhead, with a simpler searching operation, the storage density and searching energy efficiency of the CAM being improved, and also with an ability to compress the entry states when quantized as an MCAM storing multi-level entry states, making it possible to further increase the storage density of the CAM, which is of great significance for table lookup search operation based on the CAM.

A memory device includes a memory unit array on substrate, the memory unit array includes a plurality of memory units, each memory unit includes: a left and a right stack arranged at intervals in a horizontal direction. The left stack and right stacks each include a lower isolation layer, PMOS layer, first NMOS layer, upper isolation layer and second NMOS layer stacked on the substrate sequentially. The PMOS layer, and the first and second NMOS layers each include first source/drain layer, channel layer and second source/drain layer vertically stacked. The channel layer is laterally recessed relative to the first and second source/drain layers; and a gate stack between the first and second source/drain layers in the vertical direction, and disposed on opposite sides of the channel layer and embedded into a lateral recess of the channel layer.

A storage device includes a substrate, a storage unit array, and word lines extending in the first direction. The storage unit array includes storage units arranged along a first direction and a second direction. Each storage unit includes: an active region extending in a third direction and including a vertical stack of first source/drain, channel and second source/drain layers, and a gate stack between the first and second source/drain layers in a vertical direction and sandwiching the channel layer from at least two opposite sides. First source/drain layers of each column are continuous to form a bit line extending in the second direction in a zigzag shape. Each word line extends in the first direction to intersect the active regions of a respective row, and is electrically connected to the gate stack of each storage unit on two opposite sides of the channel layer.

A storage device is provided, including: a substrate; word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and a storage unit including a plurality of storage units, each of which is electrically connected to a word line and a bit line. Each storage unit includes: an active region extending in a third direction inclined with the first direction; a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and gate stacks between the first source/drain layer and the second source/drain layer, and on opposite sides of the channel layer in a fourth direction orthogonal to the third direction, to sandwich the channel layer. The word line corresponding to each storage unit extends across the storage unit in the first direction to be electrically connected to the gate stacks on opposite sides.

A high-speed and high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a capacitance-variable dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a capacitance-variable selector connected in series, by regulating the voltage division relationship of the memory cells, the voltage division of the ferroelectric capacitor in the unselected cells is reduced, so that its disturbance is reduced; and by using the capacitors in series, the RC delay of memory cells is decreased, so as to improve the memory access speed. Therefore, the disturbance of unselected cells is reduced, the storage window of the memory is improved, the bit error rate of the memory is reduced, and the memory access speed is improved, without increasing additional area overhead.

A method for manufacturing a semiconductor structure includes: forming first shallow trench isolation structures in a substrate, which isolate a plurality of active areas extending in first direction in the substrate, in which a first shallow trench isolation structure includes a sacrificial layer and a first dielectric layer stacked from bottom up in sequence; forming a plurality of word line isolation grooves in the substrate, in which a word line isolation groove is located above the sacrificial layer and extends in second direction; forming a second dielectric layer on sidewalls of the word line isolation groove, in which a pore penetrating to the substrate is provided inside the second dielectric layer; metallizing a lower part of an active area based on the pore to form a bit line extending in first direction; and removing the sacrificial layer based on the pore to form an air gap between adjacent bit lines.