Celestial AI Inc.

The present disclosure relates to example implementations of optically accessible circuit packages. For example, this disclosure includes implementations for creating a circuit package with a photonic integrated circuit (PIC) connected to electrical integrated circuit (EIC) components via an organic interposer. In many implementations, the circuit package maintains optical access to a gating coupler (GC) region on the PIC via an internal cavity area in the organic interposer. In this way, a fiber array unit (FAU) or other optical connection can couple to the circuit package to communicate data from the EIC components of the circuit package and another circuit package or an external device connected to the FAU (e.g., both send and receive data with the cp) via the open access GC region.

Systems and methods for switching are disclosed. In an example, a switching system includes a photonic integrated circuit (PIC) having optical ports, an electric integrated circuit (EIC) stacked on the PIC and having switching circuitry, and photonic transceivers optically coupled to the optical ports of the PIC and electrically coupled to the switching circuitry of the EIC, and the switching circuitry is configured to transfer digital signals, which are generated from optical signals received at a first photonic transceiver of the photonic transceivers, to a second photonic transceiver of the photonic transceivers based on information in the digital signals, wherein the first photonic transceiver is optically coupled to a first optical port of the PIC and the second photonic transceiver is optically coupled to a second optical port of the PIC.

The present invention is directed to electrical circuits. In an embodiment, the present invention provides a clock compensation device configured to correct timing discrepancies in differential clock signals. The circuit comprises positive and negative lines with multiple inverters, including crossover inverters that generate correction signals to maintain synchronization between the clock signals. There are other embodiments as well.

The present disclosure relates to implementations of a photonic circuit, and particularly to a photonic circuit that includes one or more matrix circuits. For example, the present disclosure relates to photonic circuit implementations of unitary matrices, and of arbitrary real and/or complex matrices factorized using unitary matrices, that utilize special generalized Mach-Zehnder interferometers (SGMZIs) as building blocks of various matrix circuit architectures.

Disclosed are coherent photonic circuit architectures that optically implement linear algebraic computations. In neuromorphic applications of such photonic circuit architectures, individual neural network layers can be implemented by coherent optical linear neurons in a crossbar configuration, integrated with electronic circuitry at the interfaces between neural network layers to determine the neuron inputs to one layer based on the neuron outputs of the preceding layer. Wavelength division multiplexing can be used to efficiently implement certain specific network models, optionally in conjunction with electro-optic switches to render a generic hardware configuration programmable.

Various embodiments provide for clock signal distribution within a processor, such as a machine learning (ML) processor, using a photonic fabric.

A circuit package includes a photonic integrated circuit (PIC) and four electronic integrated circuits (EIC) electrically connected to and physically overlapping a first surface of the PIC. An optical interface for coupling optical signals into and/or out of the PIC is coupled to a substrate that is attached to a second surface of the PIC opposite the first surface of the PIC. Each EIC includes an analog-mixed signal (AMS) block located at or near a geometric center of the respective EIC. The PIC includes four active regions located at respective corners of the PIC. Each active region of the PIC is coupled to the respective AMS block.

Methods, devices, and systems for driving optical modulators. An example integrated circuit includes a driver including a first circuit having a first switch coupled between a first input and a first output and a second circuit having a second switch coupled between a second input and a second output. Each of the first and second switches is configured to receive a control signal adjustable to control a corresponding signal path with a corresponding input electronic signal. The first and second circuits are configured to control a rising edge and a falling edge of an output electronic signal at an output of the driver that is based on a first output electronic signal at the first output and a second output electronic signal at the second output. The output of the driver is electrically coupled to the optical modulator to provide the output electronic signal to modulate an optical signal.

Methods, devices, and systems for driving optical modulators. An example integrated circuit includes a driver including: a first circuit having a first switch coupled between a first input and a first output and a second circuit having a second switch coupled between a second input and a second output. Each of the first and second switches is configured to receive a control signal adjustable to control a corresponding signal path with a corresponding input electronic signal. The first and second circuits are configured to control a rising edge and a falling edge of an output electronic signal at an output of the driver that is based on a first output electronic signal at the first output and a second output electronic signal at the second output. The output of the driver is electrically coupled to the optical modulator to provide the output electronic signal to modulate an optical signal.

Multi-chip electro-photonic networks for interconnecting multiple circuit packages via photonic channels. Examples of a computing system include a first circuit package, a second circuit package, and one or more inter-chip bidirectional photonic channels interconnecting the first and second circuit packages. The first circuit package can include one or more memory nodes. The second circuit package can include multiple compute nodes and intra-chip bidirectional photonic channels interconnecting the compute nodes.