Celestial AI Inc.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve techniques for packaging an electro-photonic circuit while preserving access to a grating coupler, which may involve using a sacrificial die in conjunction with a unique overmolding process.

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve techniques for packaging an electro-photonic circuit while preserving access to a grating coupler, which may involve using a sacrificial cap in conjunction with a unique overmolding process.

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve producing or manufacturing memory circuit packages having memory stacks positioned on top of electronic integrated (EIC) dies positioned over one or more PIC wafers. Techniques described herein also relate to forming overmolded memory circuit packages having optical interfaces which are optically accessible via optical window(s).

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve producing or manufacturing memory circuit packages having memory stacks positioned on top of electronic integrated (EIC) dies positioned over one or more PIC wafers. Techniques described herein also relate to forming overmolded memory circuit packages having optical interfaces which are optically accessible via optical window(s).

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve techniques for packaging an electro-photonic circuit while preserving access to a grating coupler, which may involve using a sacrificial die in conjunction with a unique overmolding process.

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve techniques for packaging an electro-photonic circuit while preserving access to a grating coupler, which may involve using a sacrificial die in conjunction with a unique overmolding process.

A method for processing a tensor is described including obtaining a first register for a number of items in the tensor. One or more second registers for a number of items in a first and a second axis of the tensor are obtained. A stride in the first and the second axis is obtained A next item in the tensor is obtained using the stride in the first axis and a first offset register, when the first register indicates the tensor has additional items to process and the second registers indicate the next item resides in the first axis. A next item in the tensor is obtained using the stride in the first axis and the second axis, the first offset register, and a second offset register. The first register and a second register is modified. The first and the second offset registers are modified.

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve producing or manufacturing wafers having circuit packages formed thereon. Techniques described herein related to modifying a dimension of wafers in order that the wafers conform to a nominal dimension, such that the wafers may be implemented in connection with processing equipment that is specifically configured to operate on wafers of the nominal dimension.

The present disclosure relates to example implementations of optically accessible circuit packages. For example, this disclosure includes implementations for creating a circuit package with a photonic integrated circuit (PIC) connected to electrical integrated circuit (EIC) components via an organic interposer. In many implementations, the circuit package maintains optical access to a gating coupler (GC) region on the PIC via an internal cavity area in the organic interposer. In this way, a fiber array unit (FAU) or other optical connection can couple to the circuit package to communicate data from the EIC components of the circuit package and another circuit package or an external device connected to the FAU (e.g., both send and receive data with the cp) via the open access GC region.