Company patents
Ceremorphic, Inc.
Ceremorphic, Inc. appears to be undergoing a significant shift in its patent strategy, with a broad decline across most categories in 2025 and so far in 2026, following a surge in 2024 where categories like Computer Hardware Architecture saw a +120.0% YoY increase. The company's focus on Cryptographic Mechanisms, however, shows a surprising resurgence with a +100.0% YoY growth in 2026, indicating a potential emerging priority despite the overall portfolio contraction.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
90 US filings (since 2023) · 12 categories · 16 themes
Novel hardware designs and processing pipelines tailored for specific computational tasks, such as graphics rendering, neural network operations, or matrix transformations, often involving custom circuits, memory arrays, or data flow mechanisms.
Specialized hardware, architectural designs, and computational methods to improve the speed, efficiency, and security of artificial intelligence and machine learning model execution, particularly for inference and data processing.
Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.
Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.
Utilizing dedicated hardware components, secure enclaves, or trusted execution environments to perform cryptographic operations, enhancing security, performance, or isolation from software vulnerabilities.
Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.
Systems and methods for encrypting data at a fine-grained level (e.g., per data unit or based on sensitivity) and controlling access to it, often involving delegated authorization, contextual policies, or secure data sharing.
Focuses on using distributed ledger technology (DLT) like blockchain to secure financial transactions, manage digital identities, or ensure data integrity and traceability across various applications.
Digital logic circuits designed to interface with analog sensors or signals, including comparators, input buffers, differential input stages, and logic for processing sensor outputs (e.g., capacitance, optical, touch) for detection or measurement.
Systems and devices that utilize controlled magnetic fields, often generated by electromagnets, to produce mechanical motion, precise positioning, or manipulate physical phenomena like plasma distribution.
Focuses on the architectural and circuit-level innovations for Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) to improve speed, accuracy, linearity, and power efficiency. Includes specific types like SAR and Delta-Sigma, and their constituent components.
Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.
Techniques for generating human-like text or other content using large pre-trained models, often involving prompt engineering, speculative decoding, or multi-modal inputs for content creation.
Techniques for designing and manufacturing compact, multi-functional magnetic components, such as inductors, transformers, and coils, often involving embedded structures, multilayer designs, or shared magnetic circuits to achieve higher power density or smaller form factors.
Involves systems designed to automatically detect errors or failures and initiate predefined or intelligent corrective actions, recovery procedures, or notifications to minimize downtime and manual intervention.
Enhancements to the physical and data link layers of network communication, focusing on hardware components, signal integrity, power efficiency, and efficient data transfer mechanisms for specific interfaces and buses.
Patents
Showing 1-3 of 3
Advanced Memory Cell Structures