Credo Technology Group Limited

An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S 1 , S 2 , and S 3 . The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.

Disclosed equalizers, transceivers, communication systems, and associated methods, provide adaptation of pre-equalizer coefficients based on at least one receive filter coefficient. One illustrative equalizer includes: a discrete-time, finite impulse response (“FIR”) filter configured to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is: configured to adjust coefficients for the FIR filter based on a performance of the equalizer, the coefficients including a first post-cursor coefficient; and configured to change a first post-cursor coefficient of a pre-equalizer if the first post-cursor coefficient of the FIR filter has a magnitude exceeding a first threshold.

Various adaptive retiming methods and apparatuses. One illustrative retimer apparatus takes the form of an integrated circuit having: at least one input contact configured to receive an input PCIe signal; a retimer module configured to convert the input PCIe signal into a digital symbol stream, and further configured to convert the digital symbol stream into a retimed PCIe signal; a multiplexer having a first selectable input configured to receive the retimed PCIe signal; a bypass path configured to provide an analog PCIe signal to a second selectable input of the multiplexer; and at least one output contact coupled to an output of the multiplexer to provide an output PCIe signal.

Phase lock loop calibration methods can be accelerated, and the accelerated method incorporated in integrated circuits and systems. One illustrative calibration method for use in a controller determines a calibrated value of a calibration parameter for a phase lock loop configured to generate a clock signal. The method includes: finding a lower bound by stepping downward from an initial value of the calibration parameter while a frequency error remains below a predetermined threshold; finding an upper bound by stepping upward from the initial value while the frequency error remains below the predetermined threshold; and using a value greater than or equal to the lower bound and less than or equal to the upper bound as the calibrated value.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

Techniques are provided for reducing crosstalk between bond wires coupling high frequency signals to multiple transducers in an integrated circuit (IC) chip. At least some of the techniques employ a bridge element configured to be bottom mounted to a printed circuit board next to a surface emitter chip. The bridge element may include: device contacts to each be bond wire connected to a respective anode contact of the surface emitter chip; board contacts to each be bond wire connected to a respective signal trace of the printed circuit board; and a signal path for each of the device contacts, the signal path connecting that device contact to a respective one of the board contacts without active amplification.

To expedite training and achieve fast linkup times, one illustrative receiver includes: a continuous time linear equalizer configured to provide a controllable amount of high frequency boost to an analog receive signal; an analog to digital converter configured to convert the analog receive signal into a digitized receive signal; a channel estimation module configured to obtain a spectral density measurement of the digitized receive signal at each of two different frequencies, the spectral density measurements having a difference indicating a slope of a channel response; and a microcontroller configured to set at least one operating parameter of the continuous time linear equalizer based on said difference. An illustrative method includes: estimating a slope of frequency dependence of a channel response; using the slope to retrieve a set of equalization parameters from a look-up table; and employing the set of equalization parameters to exit a receiver training mode.

Connectors to a set of differential transmit signal contacts for multiple lanes of a communications link may incur signal crosstalk between adjacent lanes. Similar signal crosstalk at the other end of the communications link may be incurred by connectors to a set of differential receive signal contacts. The connector arrangement may provide opposite polarities to the signal crosstalk contributions at opposite ends of the link, creating a substantial reduction in crosstalk.

Phase lock loop calibration methods can be accelerated, and the accelerated method incorporated in integrated circuits and systems. One illustrative calibration method for use in a controller determines a calibrated value of a calibration parameter for a phase lock loop configured to generate a clock signal. The method includes: finding a lower bound by stepping downward from an initial value of the calibration parameter while a frequency error remains below a predetermined threshold; finding an upper bound by stepping upward from the initial value while the frequency error remains below the predetermined threshold; and using a value greater than or equal to the lower bound and less than or equal to the upper bound as the calibrated value.

Serializer/deserializer (SerDes) modules, equalizers, and equalization techniques having robust parameter initialization may substantially reduce convergence time. One illustrative equalizer includes: a discrete-time, finite impulse response (“FIR”) filter to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is configured to, for each of multiple values in a search range, estimate a performance of the equalizer based on the channel symbols and at least one of the filtered signal or an input signal to the decision element; configured to find a centroid value based on the performance for each of the multiple parameter values in the search range; and configured to derive an initial value for the parameter from the centroid value.