Credo Technology Group Limited

An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S 1 , S 2 , and S 3 . The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.

Serializer/deserializer (SerDes) modules, equalizers, and equalization techniques having robust parameter initialization may substantially reduce convergence time. One illustrative equalizer includes: a discrete-time, finite impulse response (“FIR”) filter to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is configured to, for each of multiple values in a search range, estimate a performance of the equalizer based on the channel symbols and at least one of the filtered signal or an input signal to the decision element; configured to find a centroid value based on the performance for each of the multiple parameter values in the search range; and configured to derive an initial value for the parameter from the centroid value.

Flash analog to digital converters and other types of integrated circuits having multiple comparators may employ calibration methods and firmware to efficiently compensate the various offset voltages of the multiple comparators. One illustrative integrated circuit includes: multiple comparators each configured to provide a comparator output signal indicating whether an input signal exceeds a reference voltage by more than an offset voltage, the multiple comparators including a current comparator and a previous comparator; and a controller configured to perform a search to select a calibration setting for each of the comparators in turn, the controller determining an initial search window for the current comparator based on a calibration setting selected for the previous comparator.

Integrated circuit transceivers having digital timing recovery loops with phase interpolation may incorporate dynamic loop gains to compensate for nonlinearities of the phase interpolation. An illustrative receiver circuit includes: a phase interpolator, a sampling element, a timing error estimator, and a feedback circuit. The phase interpolator provides a sampling signal by applying a phase shift to a clock signal in response to a phase control signal. The sampling element produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal. The timing error estimator produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal. The feedback circuit derives the phase control signal from the timing error signal using a scaling element configured to scale the estimated timing error by a scale factor that depends on the phase control signal.

Serializer/deserializer (SerDes) modules, equalizers, and equalization techniques having robust parameter initialization may substantially reduce convergence time. One illustrative equalizer includes: a discrete-time, finite impulse response (“FIR”) filter to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is configured to, for each of multiple values in a search range, estimate a performance of the equalizer based on the channel symbols and at least one of the filtered signal or an input signal to the decision element; configured to find a centroid value based on the performance for each of the multiple parameter values in the search range; and configured to derive an initial value for the parameter from the centroid value.

An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S 1 , S 2 , and S 3 . The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.

Receivers, methods, and cores, can provide decision feedback equalization with efficient burst error correction. An illustrative receiver includes: a decision feedback equalizer that derives symbol decisions from a receive signal; a subtractor that determines an equalization error for each said symbol decision; and a post-processor that operates on the symbol decisions and equalization error to detect and correct symbol decision errors. An illustrative receiving method includes: using a decision feedback equalizer to derive symbol decisions from a filtered receive signal; determining an equalization error for each said symbol decision; and processing the symbol decisions and equalization error to detect and correct symbol decision errors. An illustrative semiconductor intellectual property core generates circuitry for implementing a receiving and method as described above.

Disclosed successive approximation register analog-to-digital converters (SAR ADCs) and conversion methods detect a statistical effect of meta-stability induced errors and limit the level of such errors. One illustrative integrated circuit chip includes: a SAR ADC that employs asynchronous bit cycles to convert a sequence of analog signal samples into a sequence of digital signal samples; and a detector that accelerates the asynchronous bit cycles when a meta-stability error bias exceeds a predetermined threshold. An illustrative analog-to-digital conversion method includes: converting a sequence of analog signal samples to a sequence of digital signal samples using a successive approximation register analog to digital converter (SAR ADC) with asynchronous bit cycles; deriving a meta-stability error bias from the sequence of digital signal samples; and accelerating the asynchronous bit cycles when the meta-stability error bias exceeds a predetermined threshold.

Receivers and receiving methods having maximum likelihood sequence detection with pseudo partial response equalization. One illustrative receiver includes: a feedforward equalizer that produces an equalized receive signal by diminishing a receive signal's intersymbol interference; a decision element that derives initial symbol decisions from samples of the equalized receive signal; and a filter that applies a partial response to the equalized receive signal or to an equalization error signal to produce input for a maximum likelihood sequence detector (MLSD). The MLSD may be a reduced complexity detector that derives a final sequence of symbol decisions by evaluating state metrics only for each initial symbol decision and its competing symbol decision.

Receivers and receiving methods having maximum likelihood sequence detection with pseudo partial response equalization. One illustrative receiver includes: a feedforward equalizer that produces an equalized receive signal by diminishing a receive signal's intersymbol interference; a decision element that derives initial symbol decisions from samples of the equalized receive signal; and a filter that applies a partial response to the equalized receive signal or to an equalization error signal to produce input for a maximum likelihood sequence detector (MLSD). The MLSD may be a reduced complexity detector that derives a final sequence of symbol decisions by evaluating state metrics only for each initial symbol decision and its competing symbol decision.