Cryptography Research, Inc.

An application executing at a first platform receives, from a tester device, a first request to generate a secure data asset. Responsive to authenticating the client, the application sends, to a second platform, a second request to determine whether the client has access to the secure data asset. Responsive to receiving an indication, from the second platform, that the client has access to the secure data asset, the application performs one or more operations to generate the secure data asset. The application sends, to the tester device, the generated secure data asset.

Disclosed systems and techniques include a cryptographic processor for processing of both unprotected data and protected data using an unprotected data path. In one implementation, the cryptographic processor includes a processing unit, and a control unit to selectively cause the processing unit to operate in a public mode or a secure mode. In the public mode, the processing unit performs a computational operation to compute a nonlinear function of a public data. In the secure mode, the processing unit computes, over a plurality of iterations, a plurality of shares of the nonlinear function of a secure data. At each iteration, the processing unit performs multiple instances of the computational operation to compute a respective share of the nonlinear function of the secure data.

Helper data and/or physically unclonable function (PUF) output data may be analyzed to determine which bits of the raw PUF output are stable. A first subset of the stable PUF output bits are selected (e.g., randomly) to generate a first stable PUF output value to be used as a first device unique value. To change the device unique value (a.k.a., digital fingerprint or fingerprint) of the integrated circuit generated by the PUF circuitry, new subsets (which may be generated off-chip) with different stable PUF output bits may be provided to the integrated circuit (i.e., provisioned) from time to time (e.g., with a new firmware/software update, after some arbitrary period of time—e.g., one year—etc.). Each new and different subset of stable bits used by the integrated circuit causes the integrated circuit to generate new, and different, device unique values.

Aspects of the present disclosure involve a method and a system to execute the method to perform a cryptographic operation involving a modulo N computation, the method comprising loading a first integer number and a second integer number, wherein the first integer number and the second integer number are within an interval of 2N integer numbers, and performing an arithmetic operation involving the first integer number and the second integer number, wherein the arithmetic operation is to produce a third integer number, and wherein the arithmetic operation comprises a shifting operation to ensure that the third integer number is inside the interval of 2N integer numbers.

Multiple (e.g., two) hosts access a single memory channel (and/or device) via a memory controller. The single memory channel/device can support at most one access at a time. To reduce contention between the multiple hosts, the memory controller comprises multiple (e.g., two), independent, host ports. Each host port is associated with a write buffer(s) in the memory controller that stores write data at least until the memory controller writes the data to the memory channel. Data stored in a write buffer may be used to respond to memory access commands (e.g., reads or writes) on the ports without accessing the memory channel. In this manner, the hosts do not directly contend with each other for the single memory channel or the memory controller.

Technologies for protecting a secure context in a hardware root of trust (ROT) are described. One hardware ROT includes key generation logic and a cryptographic circuit. The key generation logic generates a first key from a value, corresponding to a physical variation of the hardware ROT, and first helper data associated with the physical variation of the hardware ROT. The key generation logic generates a second key from the value and second helper data associated with the physical variation of the hardware ROT. The cryptographic circuit receives a first encrypted secure context from off-chip storage and decrypts the first encrypted secure context using the first key to obtain a secure context. The cryptographic circuit encrypts the secure context using the second key to obtain a second encrypted secure context and stores the second encrypted secure context in the off-chip storage.

Disclosed aspects and implementations are directed to systems and techniques for protecting cryptographic operations using change-of-variable transformation, from a first variable to a second variable, of a first polynomial obtained using an input into a cryptographic operation and a second polynomial obtained using a cryptographic key for the cryptographic operation, performing a joint operation using the transformed first polynomial and the transformed second polynomial, and computing an output of the cryptographic operation using an output of the joint operation.

Systems and techniques for cryptographically protecting data in a computer memory are disclosed. The techniques include dividing the data into a first portion and a second portion, encrypting the first portion of the data to create a first stored form of the data, encrypting the second portion of the data, and storing, in the computer memory, the first stored form of the data and a second stored form of the data. The techniques include, to encrypt the second portion, calculating a hash based on the first stored form of the data, applying a first pseudorandom function to the hash to obtain a bit sequence, and combining the bit sequence with the second portion of the data to obtain the second stored form of the data.

Technologies for protecting data integrity of an authentication algorithm using intermediate states are described. One inline memory encryption (IME) engine performs an authentication algorithm that uses a hash function to compute an authentication tag. The IME engine includes integrity-protection logic to store an intermediate state of a tag computation and incoming data segments. In the event of an error in the computation, the integrity-protection logic can compute the intermediate state again using a last intermediate state and the last data segment.

Disclosed aspects and implementations are directed to systems and techniques for multi-counter memory encryption with targeted access of individual memory blocks. In one example, replacing a stored block in a memory device includes encrypting a replacement block using a first initialization vector (IV) having a block counter associated with a number of times the stored block has been previously replaced, replacing the stored block with the encrypted replacement block in the memory device, encrypting a second IV to obtain a tag encryption vector, the second IV including a tag counter associated with a number of times an authentication tag for a plurality of blocks has been previously updated, and updating, using the encrypted second IV, the authentication tag for the plurality of blocks.