UnfoldIPThemes

Company patents

Cryptography Research, Inc.

Cryptography Research, Inc. appears to be significantly scaling back its patenting efforts across its core areas, with its largest category, Cryptographic Mechanisms (62.8% of portfolio), experiencing a -11.5% decline in 2025 and a substantial -60.9% decline so far in 2026, while Computer Security (43.8% of portfolio) also saw a -13.3% decline in 2025 and a -38.5% decline so far in 2026, indicating a broad shift away from active patenting in these foundational domains.

Patent Trend by Technology Area

Yearly patent publications since 2023

Product themes

Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.

137 US filings (since 2023) · 9 categories · 13 themes

Hardware-Assisted Cryptographic Operations

Utilizing dedicated hardware components, secure enclaves, or trusted execution environments to perform cryptographic operations, enhancing security, performance, or isolation from software vulnerabilities.

Cryptographic Mechanisms
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69since 2023
-9.5%YoY
Granular Data Encryption & Access Control

Systems and methods for encrypting data at a fine-grained level (e.g., per data unit or based on sensitivity) and controlling access to it, often involving delegated authorization, contextual policies, or secure data sharing.

Cryptographic Mechanisms
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50since 2023
0.0%YoY
Secure Data Storage & Provenance

Techniques for protecting data at rest or in backup, ensuring its integrity, confidentiality, and verifiable origin, often involving encryption, unique identifiers, or secure repositories.

Computer SecurityNetwork Security & Access Control
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24since 2023
-60.0%YoY
AI/ML for Cryptographic Security

Applying artificial intelligence and machine learning techniques to enhance cryptographic systems, such as generating encryption models, improving zero-trust architectures, or enabling privacy-preserving computations like federated learning.

Computer SecurityCryptographic Mechanisms
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16since 2023
+40.0%YoY
Memory System Performance & Reliability

Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.

Computer Hardware Architecture
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16since 2023
+50.0%YoY
Secure Key Management & Rotation

Methods and systems for generating, distributing, updating, rotating, and securely destroying cryptographic keys to maintain data confidentiality and integrity over time, including quantum key distribution.

Cryptographic Mechanisms
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15since 2023
-20.0%YoY
Homomorphic Encryption Acceleration

Techniques for improving the performance, efficiency, or practicality of fully homomorphic encryption (FHE) schemes, often involving hardware accelerators or optimized algorithms for operations like bootstrapping and key-switching.

Cryptographic Mechanisms
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13since 2023
-20.0%YoY
Access Control & Identity Management

Systems and methods for authenticating users, devices, or applications, authorizing their access to resources based on policies, and managing digital identities across various platforms.

Network Security & Access ControlComputer Security
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11since 2023
new
Specialized Compute Architecturesfiltered

Novel hardware designs and processing pipelines tailored for specific computational tasks, such as graphics rendering, neural network operations, or matrix transformations, often involving custom circuits, memory arrays, or data flow mechanisms.

Computer Hardware Architecture
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9since 2023
0.0%YoY
Secure Data Sharing & Rights Management

Mechanisms to facilitate the secure exchange of data between different entities or systems while enforcing usage policies, managing digital content rights, and ensuring data consistency during replication or transfer.

Computer Security
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3since 2023
new
On-Chip Power Management & Protection

Integrated circuits or sub-circuits designed to regulate, balance, or protect power delivery within a device, often involving specific transistor and capacitor arrangements.

Computer Hardware Architecture
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3since 2023
0.0%YoY
Cloud Security Posture Management

Tools and processes for assessing, monitoring, and improving the security configuration and external accessibility of resources deployed within cloud computing environments.

Network Security & Access Control
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2since 2023
new
Location-Aware Mobile Services

Mobile applications and systems leveraging wireless communication and location data (e.g., GPS, RFID, geo-fencing) to provide context-specific services, transactions, or user interactions.

Wireless Networks
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1since 2023
n/a

Patents

Showing 1-9 of 9

Specialized Compute Architectures
Page 1 of 1
US 12393679 B2GRANTED
G06F21/55

Protection of neural networks by obfuscation of neural network operations and architecture

Filed:2021-12-16Pub:2025-08-19
Applicant:CRYPTOGRAPHY RESEARCH, INC.

Aspects of the present disclosure involve implementations that may be used to protect neural network models against adversarial attacks by obfuscating neural network operations and architecture. Obfuscation techniques include obfuscating weights and biases of neural network nodes, obfuscating activation functions used by neural networks, as well as obfuscating neural network architecture by introducing dummy operations, dummy nodes, and dummy layers into the neural networks.

US 12332732 B2GRANTED
G06F11/00

Pipelined hardware error classification and handling

Filed:2022-12-08Pub:2025-06-17
Applicant:Cryptography Research, Inc.

Technologies for detecting and classifying errors detected in pipelined hardware are described. One device includes a hardware pipeline with a set of pipeline stages. Error detection logic can detect an error in the hardware pipeline, and control logic can classify the error in one of the multiple categories based on a type of the error, a position of the first data in a data stream that triggered the error, and a position of a pipeline stage in which the error is detected. The control logic can perform an error-response action based on the error classification of the error.

US 20250106022 A1APPLICATION
H04L9/30

MULTI-LANE CRYPTOGRAPHIC ENGINE AND OPERATIONS THEREOF

Filed:2022-07-13Pub:2025-03-27
Applicant:CRYPTOGRAPHY RESEARCH, INC.

Aspects of the present disclosure involve a cryptographic processor that includes four or more multiplication circuits, two or more addition circuits, and two or more memory circuits. The cryptographic engine is configured to perform a variety of operations, including modular multiplication, modular inversion, matrix multiplication, Montgomery multiplication, computations of Jacobi symbols, and the like. The cryptographic engine support streaming computations where at least some of the multiplication circuits operate on multipliers and/or multiplicands that are also used during other cycles of computations.

US 20250036726 A1APPLICATION
G06F21/14

PROTECTION OF NEURAL NETWORKS BY OBFUSCATION OF NEURAL NETWORK ARCHITECTURE

Filed:2024-08-05Pub:2025-01-30
Applicant:CRYPTOGRAPHY RESEARCH, INC.

Aspects of the present disclosure involve implementations that may be used to protect neural network models against adversarial attacks by obfuscating neural network operations and architecture. Obfuscation techniques include obfuscating weights and biases of neural network nodes, obfuscating activation functions used by neural networks, as well as obfuscating neural network architecture by introducing dummy operations, dummy nodes, and dummy layers into the neural networks.

US 20240370229 A1APPLICATION
G06F7/544

MULTI-LANE CRYPTOGRAPHIC ENGINES WITH SYSTOLIC ARCHITECTURE AND OPERATIONS THEREOF

Filed:2022-07-14Pub:2024-11-07
Applicant:CRYPTOGRAPHY RESEARCH, INC.

Aspects of the present disclosure involve a cryptographic processor that includes a systolic array having a plurality of processing lanes (PLs), each PL including a systolic sub-array of two or more processing elements (PEs), each PE being configured to multiply two numbers to obtain and store a multiplication product. The cryptographic processor is configured to efficiently perform a variety of operations, including multiplication of large numbers, modular reduction, Montgomery reduction, and the like.

US 12099622 B2GRANTED
G06F21/62

Protection of neural networks by obfuscation of activation functions

Filed:2021-12-16Pub:2024-09-24
Applicant:Cryptography Research, Inc.

Aspects of the present disclosure involve implementations that may be used to protect neural network models against adversarial attacks by obfuscating neural network operations and architecture. Obfuscation techniques include obfuscating weights and biases of neural network nodes, obfuscating activation functions used by neural networks, as well as obfuscating neural network architecture by introducing dummy operations, dummy nodes, and dummy layers into the neural networks.

US 12056219 B2GRANTED
G06F21/14

Protection of neural networks by obfuscation of neural network architecture

Filed:2021-12-16Pub:2024-08-06
Applicant:Cryptography Research, Inc.

Aspects of the present disclosure involve implementations that may be used to protect neural network models against adversarial attacks by obfuscating neural network operations and architecture. Obfuscation techniques include obfuscating weights and biases of neural network nodes, obfuscating activation functions used by neural networks, as well as obfuscating neural network architecture by introducing dummy operations, dummy nodes, and dummy layers into the neural networks.

US 20240078308 A1APPLICATION
G06F21/55

PROTECTION OF NEURAL NETWORKS BY OBFUSCATION OF NEURAL NETWORK OPERATIONS AND ARCHITECTURE

Filed:2021-12-16Pub:2024-03-07
Applicant:CRYPTOGRAPHY RESEARCH, INC.

Aspects of the present disclosure involve implementations that may be used to protect neural network models against adversarial attacks by obfuscating neural network operations and architecture. Obfuscation techniques include obfuscating weights and biases of neural network nodes, obfuscating activation functions used by neural networks, as well as obfuscating neural network architecture by introducing dummy operations, dummy nodes, and dummy layers into the neural networks.

US 20230195553 A1APPLICATION
G06F11/07

PIPELINED HARDWARE ERROR CLASSIFICATION AND HANDLING

Filed:2022-12-08Pub:2023-06-22
Applicant:Cryptography Research, Inc.

Technologies for detecting and classifying errors detected in pipelined hardware are described. One device includes a hardware pipeline with a set of pipeline stages. Error detection logic can detect an error in the hardware pipeline, and control logic can classify the error in one of the multiple categories based on a type of the error, a position of the first data in a data stream that triggered the error, and a position of a pipeline stage in which the error is detected. The control logic can perform an error-response action based on the error classification of the error.

1