Empower Semiconductor, Inc.

A power converter circuit is disclosed. In one aspect, the power converter circuit includes a power input terminal, a first output terminal and a second output terminal, a plurality of capacitors coupled to the power input terminal, the first output terminal and the second output terminal, a plurality of switches coupled to the plurality of capacitors and arranged to repetitively cycle the plurality of capacitors between a first configuration and a second configuration to generate a first output voltage at the first output terminal and a second output voltage at the second output terminal, and where the circuit is arranged to limit a maximum voltage applied to each of the plurality of capacitors and switches to a fraction of a voltage at the power input terminal.

A system is disclosed. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip.

A power converter circuit is disclosed. In one aspect, the power converter circuit includes a power input terminal, a first output terminal and a second output terminal, a plurality of capacitors coupled to the power input terminal, the first output terminal and the second output terminal, a plurality of switches coupled to the plurality of capacitors and arranged to repetitively cycle the plurality of capacitors between a first configuration and a second configuration to generate a first output voltage at the first output terminal and a second output voltage at the second output terminal, and where the circuit is arranged to limit a maximum voltage applied to each of the plurality of capacitors and switches to a fraction of a voltage at the power input terminal.

A switched-mode power regulator circuit has four solid-state switches connected in series and a capacitor and an inductor that regulate power delivered to a load. The solid-state switches are operated such that a voltage at the load is regulated by repetitively (1) charging the capacitor causing a current to flow in the inductor and (2) discharging the capacitor causing current to flow in the inductor. The power regulator circuit may be configured to operate with zero current switching at frequencies in the range of 100 MHz, enabling it to be fabricated on a unitary silicon die along with the load that it powers.

A circuit. In one aspect, the circuit includes a power input terminal and an output terminal, a high-side circuit coupled between the power input terminal and the output terminal, where the high-side circuit includes a first plurality of serially connected switches, and a low-side circuit coupled between the output terminal and a ground, where the low-side circuit includes a second plurality of serially connected switches, where a first voltage between the power input terminal and the output terminal is distributed across the first plurality of serially connected switches, where a second voltage between the output terminal and the ground is distributed across the second plurality of serially connected switches. In another aspect, the high-side and low-side circuits are arranged to limit a maximum voltage applied to each of the first plurality of switches and second plurality of switches to a fraction of a voltage at the power input terminal.

A power circuit is disclosed. The power circuit includes an input node, a plurality of inductors each connected to an output node, a plurality of phases each configured to provide current to one of the inductors, and a control circuit configured to trigger the phases. The phases are configured to provide current to one of the inductors in response to being triggered by the control circuit, the control circuit is configured to determine a variable time difference between a first phase being triggered and a second phase being triggered, and the time difference is based at least in part on a voltage difference between an input voltage at the input node and an output voltage at the output node.

A power conversion device includes: a semiconductor substrate; a plurality of controllers formed on the semiconductor substrate; two or more converter phases formed on the semiconductor substrate; two or more programmable components formed on the semiconductor substrate, each of the programmable components connected to a respective one of the two or more converter phases; and an interconnect circuit formed on the semiconductor substrate. The two or more programmable components are programmable to selectively couple the two or more converter phases to the plurality of controllers via the interconnect circuit.

A multiphase switching voltage regulator is disclosed. The regulator includes a first clock generator circuit configured to receive a reference clock, and to generate M first clocks, where the M first clocks are phase separated by 360°/M, a plurality of phase extrapolator circuits, where the plurality of phase extrapolator circuits includes N phase extrapolator circuits, and a phase selector multiplexer configured to provide one of the M first clocks to each of the phase extrapolator circuits, where the N phase extrapolator circuits are configured to generate N output clocks, where the N output clocks are phase separated by 360°/N.

A circuit. In one aspect, the circuit includes a first power stage including a first switch having a first gate terminal, a first drain terminal and a first source terminal, and a second switch having a second gate terminal, a second drain terminal and a second source terminal, the first source terminal coupled to the second drain terminal, and a second power stage including a third switch having a third gate terminal, a third drain terminal and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the third source terminal coupled to the fourth drain terminal, where the second power stage is coupled in parallel to the first power stage such that the first drain terminal is couped to the third drain terminal and the second source terminal is connected to the fourth source terminal.

A switched-mode power regulator circuit has four solid-state switches connected in series and a capacitor and an inductor that regulate power delivered to a load. The solid-state switches are operated such that a voltage at the load is regulated by repetitively (1) prefluxing the inductor then charging the capacitor causing an increased current to flow in the inductor and (2) prefluxing the inductor then discharging the capacitor causing increased current to flow in the inductor. The inductor prefluxing steps enable the circuit to provide increased output voltage and/or increased output current.