Company patents

EV GROUP E. THALLNER GMBH

EV GROUP E. THALLNER GMBH's patent strategy is heavily concentrated in Semiconductor Manufacturing Process, representing 51.3% of its portfolio, though this category has seen a significant decline in recent filings, with a -77.8% YoY drop in 2026 so far. Surprisingly, despite a broad focus on semiconductor technologies, several categories like Photolithography, Layered Products (Laminates, Films), and Semiconductor Packaging & Encapsulation have seen a complete cessation of filings in 2026, each with a -100.0% YoY decline, indicating a potential shift in R&D priorities.

Patent Trend by Technology Area

Yearly patent publications since 2023

Product themes

Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.

78 US filings (since 2023) · 12 categories · 14 themes

Temporary Wafer Bonding & Debonding

Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.

Semiconductor Manufacturing ProcessChip-to-Chip Interconnect (Bonding, Bumps)
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41since 2023
-42.9%YoY
Wafer Handling and Process Environment Control

Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.

Semiconductor Manufacturing Process
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21since 2023
-14.3%YoY
Substrate Patterning & Processing

Methods and equipment for applying photoresist uniformly onto wafers, forming patterns through various exposure techniques (e.g., direct imaging, multi-exposure), and integrating patterned layers into semiconductor structures or packaging.

Photolithography
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14since 2023
+300.0%YoY
Advanced Metallization & Contacts

Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.

Chip-to-Chip Interconnect (Bonding, Bumps)
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7since 2023
n/a
Lithography Metrology & Inspection

Techniques and apparatus for measuring critical dimensions, overlay accuracy, defect detection, and surface topography in lithographic processes, often involving optical, laser, or charged particle beams.

Photolithography
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6since 2023
new
Advanced Etching & Patterning Control

Techniques for precise material removal, pattern shaping, and controlling etch selectivity or uniformity, often involving plasma, wet chemistry, or directed beams to achieve desired features on semiconductor substrates.

Semiconductor Manufacturing Process
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5since 2023
-66.7%YoY
Advanced Mask Technologies

Innovations in the design, materials, and manufacturing of lithography masks, including reflective masks, programmable masks, and defect mitigation strategies, to enable finer feature patterning and process control.

Photolithography
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4since 2023
+100.0%YoY
Interconnect Materials & Reliability

Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.

Chip-to-Chip Interconnect (Bonding, Bumps)
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4since 2023
n/a
Multi-material Product Integration & Finishing

Techniques for combining multiple materials or layers, often with specialized surface treatments, coatings, or assembly methods, to create functional or aesthetically enhanced plastic articles, including consumer goods and encapsulated electronics.

Plastics Shaping & Molding
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2since 2023
new
3D Die Stacking & Vertical Interconnects

Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.

Semiconductor Packaging & Encapsulation
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2since 2023
n/a
Chemical Mechanical Planarization & Wet Surface Treatment

Processes involving chemical and mechanical forces to planarize surfaces (CMP) or wet chemical treatments for cleaning, etching, or material removal, often utilizing specialized compositions, nozzles, or fluid management systems.

Semiconductor Manufacturing Process
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1since 2023
n/a
Plastic Extrusion Processes

Methods and equipment for continuously shaping plastic materials by forcing them through a die, often involving screw extruders, heating elements, and downstream calibration.

Plastics Shaping & Molding
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1since 2023
n/a
Thermoplastic Compression Molding

Processes involving the application of heat and pressure to shape thermoplastic or elastomeric materials, often using molds or presses, to achieve specific forms or material properties.

Plastics Shaping & Molding
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1since 2023
n/a
Precision Motion Metrology

Systems and methods for accurately measuring and compensating for position, orientation, and movement errors in mechanical systems, often for manufacturing, robotics, or optical alignment.

Length / Distance Measurement
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1since 2023
n/a

Patents

Showing 81-90 of 386

Page 9 of 39
US 20220390356 A1APPLICATION
G01N21/21

DEVICE AND METHOD FOR MEASURING A SUBSTRATE

Filed:2019-11-28Pub:2022-12-08
Applicant:EV Group E. Thallner GmbH

The invention relates to a method for measuring a multilayered substrate (1, 1′, 1″), particularly with at least one structure ( 7, 7′, 7″, 7′″, 7 IV , 7 V ) with critical dimensions, particularly with a surface structure ( 7, 7′, 7″, 7′″, 7 IV , 7 V ) with critical dimensions, characterized in that the method has at least the following steps, particularly the following procedure: producing ( 110 ) the substrate ( 1, 1′, 1″ ) with a plurality of layers ( 2, 3, 4, 5, 6, 6′, 6″ ), particularly with a structure ( 7, 7′, 7″, 7′″, 7 IV , 7 V ), particularly with a structure ( 7, 7′, 7″, 7″′, 7 IV , 7 V ) on a surface ( 6 o, 6′ o, 6″ o ) of an uppermost layer ( 6, 6′, 6″ ), wherein the dimensions of the layers and in particular the structures are known, measuring ( 120 ) the substrate ( 1, 1′, 1″ ), and in particular the structure ( 7, 7′, 7″, 7′″, 71 IV , 7 V )) using at least one measuring technology, creating ( 130 ) a simulation of the substrate using the measurement results from the measurement of the substrate ( 1, 1′, 1″ ), comparing ( 140 ) the measurement results with simulation results from the simulation of the substrate ( 1, 1′, 1″ ), optimizing the simulation ( 130 ) and renewed creation ( 130 ) of a simulation of the substrate using the measurement results from the measurement of the substrate ( 1, 1′, 1″ ), in the event that there is a deviation of the measurement results from the simulation results, or calculating (150) parameters of further substrates, in the event that the measurement results correspond to the simulation results.

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