Hangzhou Silicon-Magic Semiconductor Technology Co., Ltd.

Disclosed is a silicon carbide MOSFET device and a manufacturing method thereof. The manufacturing method comprises: forming a source region in an epitaxial layer; forming a body region in the epitaxial layer; forming a gate structure, comprising a gate dielectric layer, a gate conductor layer and an interlayer dielectric layer; forming an opening in the interlayer dielectric layer to expose the source region; forming a source contact connected to the source region via the opening, wherein an ion implantation angle of the ion implantation process is controlled to make a transverse extension range of the body region larger than a transverse extension range of the source region, so that a channel that extends transversely is formed by a portion, which is peripheral to the source region, of the body region, and at least a portion of the gate conductor layer is located above the channel.

Disclosed is a trench-type power device and a manufacturing method thereof. The trench-type power device comprises: a semiconductor substrate; a drift region located on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode. The trench-type power device adopts a double-trench structure, which combines a trench-type MOSFET with the Schottky barrier diode and forms the Schottky metal on the side wall of the trench, so that the performance of the power device can be improved, and the unit area of the power device can be reduced.

A switched-capacitor converter with power delivery regulation, includes: a switched-capacitor module having switches and capacitors, converting an input voltage into an output voltage according to a conversion ratio corresponding to a coupling structure of the capacitors generated through switching switches; a control voltage generator that generates a control voltage by comparing a preset reference value with a feedback signal selected from an input current flowing to the switched-capacitor module, an output current, and an output voltage of the switched-capacitor module; and a upper switch turn-on resistance regulator that creates a regulated voltage applied to a gate terminal of an upper switch by adjusting a drive voltage for driving the upper switch according to the control voltage, adjust ON-resistance of the upper switch by applying the regulated voltage to the gate terminal to control a gate-source voltage, and regulates power delivered by the switched-capacitor module through an adjustment of the ON-resistance.

A semiconductor device having: a base layer including transistor regions and diode regions alternately arranged along a predetermined direction; first trenches formed in the transistor regions, wherein in each one of the first trenches, a control gate polysilicon layer is formed in an upper portion of the first trench, sidewalls and a bottom of the control gate polysilicon layer are wrapped by a control gate oxide layer; and second trenches formed in the diode regions, wherein in each one of the second trenches, a third gate polysilicon layer is formed in an upper portion of the second trench, sidewalls and a bottom of the third gate polysilicon layer are wrapped by a third gate oxide layer; wherein a thickness of the control gate oxide layer is greater than the third shielded gate oxide layer.

A silicon carbide power semiconductor device is provided, including a substrate, a drift region, a body region, a source region, a base region, a shielding region, a JFET region, a gate structure, an insulating layer, and a source metal layer. The source contacting window has first edges within second edges of the body region corresponding to the first edges, and the source metal layer abuts only a part of the source region. The area of the silicon carbide power semiconductor device of the present disclosure is thus reduced. Therefore, the ratio of the channel length to the area of the silicon carbide power semiconductor device and the ratio of the area of the JFET region to the area of the silicon carbide power semiconductor device are increased, whereby the specific on-resistance of the silicon carbide power semiconductor device is reduced.

The present disclose relates to a SiC MOSFET device and a manufacturing method thereof. The method includes providing a semiconductor base of a first doping type; forming a patterned first barrier layer on an upper surface; forming a source region extending from the upper surface to the interior of the semiconductor base by taking the first barrier layer as a mask, wherein the source region is of the first doping type; etching a part of the first barrier layer to form a second barrier layer, and allowing anion implantation window of the second barrier layer to be larger than the ion implantation window of the first barrier layer; forming a first type base region by taking the second barrier layer as a mask, wherein the first type base region is of a second doping type; and forming a contact region of the second doping type.

A charge pump having a first capacitor, a current controlling transistor and an overcurrent protection circuit. The first capacitor has a first terminal and a second terminal. The current controlling transistor has a first terminal coupled to the first terminal of the first capacitor, and a second terminal coupled to a ground reference. The overcurrent protection circuit has a current source and a bias transistor. The current source has a first terminal coupled to a power supply. The bias transistor has a first terminal coupled to a second terminal of the current source, a second terminal coupled to the ground reference, and a control terminal coupled to both the first terminal of the bias transistor and a control terminal of the current controlling transistor.

A bias circuit having a first current source, a second current source, a first current mirror circuit, a second current mirror circuit, a third current mirror circuit and a fourth current mirror circuit. The first current mirror circuit has a first transistor and a second transistor. The first current mirror circuit and the second current mirror circuit are configured to guarantee equal voltages at the drain terminals and equal voltages at the source terminals of the first and second transistors, such that the first current mirror circuit has high precision and the bias circuit has a large input voltage range.

A semiconductor device having a first epitaxial layer of a first doping type, a second epitaxial of a second doping type and a third epitaxial layer of the first doping type. A first trench and a second trench vertically extend from a first surface of the third epitaxial layer into the third epitaxial layer. A body region of the second doping type arranged in the third epitaxial layer. A body contact region of the second doping type surrounding the body region. A buried region of the second doping type connecting a portion of the body region between the first trench and the second trench to the body contact region.

A method for manufacturing a trench MOSFET includes: forming a trench extending from an upper surface of an epitaxial layer of a first dopant type into the epitaxial layer; forming a gate dielectric layer and a gate conductor located in the trench; forming a body region of a second dopant type located in the epitaxial layer, where the body region is adjacent to the trench; forming a source region of the first dopant type located in the body region; forming a first dielectric layer on the source region and the gate dielectric layer; forming a contact hole extending through the first dielectric layer and the source region and extending into the body region; forming a spacer on a side wall of the contact hole; forming a body contact region of the second dopant type through the contact hole; and forming a conductive channel filling the contact hole.