Hangzhou Silicon-Magic Semiconductor Technology Co., Ltd.

A semiconductor device having: a base layer including transistor regions and diode regions alternately arranged along a predetermined direction; first trenches formed in the transistor regions, wherein in each one of the first trenches, a control gate polysilicon layer is formed in an upper portion of the first trench, sidewalls and a bottom of the control gate polysilicon layer are wrapped by a control gate oxide layer; and second trenches formed in the diode regions, wherein in each one of the second trenches, a third gate polysilicon layer is formed in an upper portion of the second trench, sidewalls and a bottom of the third gate polysilicon layer are wrapped by a third gate oxide layer; wherein a thickness of the control gate oxide layer is greater than the third shielded gate oxide layer.

A silicon carbide power semiconductor device is provided, including a substrate, a drift region, a body region, a source region, a base region, a shielding region, a JFET region, a gate structure, an insulating layer, and a source metal layer. The source contacting window has first edges within second edges of the body region corresponding to the first edges, and the source metal layer abuts only a part of the source region. The area of the silicon carbide power semiconductor device of the present disclosure is thus reduced. Therefore, the ratio of the channel length to the area of the silicon carbide power semiconductor device and the ratio of the area of the JFET region to the area of the silicon carbide power semiconductor device are increased, whereby the specific on-resistance of the silicon carbide power semiconductor device is reduced.

A semiconductor device having a first epitaxial layer of a first doping type, a second epitaxial of a second doping type and a third epitaxial layer of the first doping type. A first trench and a second trench vertically extend from a first surface of the third epitaxial layer into the third epitaxial layer. A body region of the second doping type arranged in the third epitaxial layer. A body contact region of the second doping type surrounding the body region. A buried region of the second doping type connecting a portion of the body region between the first trench and the second trench to the body contact region.

A method for manufacturing a trench MOSFET includes: forming a trench extending from an upper surface of an epitaxial layer of a first dopant type into the epitaxial layer; forming a gate dielectric layer and a gate conductor located in the trench; forming a body region of a second dopant type located in the epitaxial layer, where the body region is adjacent to the trench; forming a source region of the first dopant type located in the body region; forming a first dielectric layer on the source region and the gate dielectric layer; forming a contact hole extending through the first dielectric layer and the source region and extending into the body region; forming a spacer on a side wall of the contact hole; forming a body contact region of the second dopant type through the contact hole; and forming a conductive channel filling the contact hole.

The trench capacitor includes a semiconductor substrate, a trench array and at least one capacitor layer. The trench array has at least one trench segment disposed in the semiconductor substrate. Each one of the at least one trench segment comprises a plurality of inner trenches oriented lengthwise along a same direction, and a side trench bordering an outer edge of each one of the at least one trench segment. The inner trenches and the side trench in each one of the at least one trench segment are communicated with each other. The at least one capacitor layer conformally lines a surface of the semiconductor substrate which has the trench array. Each one of the at least one capacitor layer includes a dielectric layer and a conducting layer disposed on the dielectric layer.

A trench gate semiconductor device having a substrate, an epitaxial layer, at least one first trench gate structure and at least one second trench gate structure. The epitaxial layer is formed on the substrate. The at least one first trench gate structure and the at least one second trench gate structure are formed in the epitaxial layer. The at least one first trench gate structure has a first depth. The at least one second trench gate structure has a second depth. The first depth is greater than the second depth. The at least one first trench gate structure and the at least one second trench gate structure are arranged alternately in a line along a first direction, and the neighboring first trench gate structure and second trench gate structure adjoins each other.

A super-junction VDMOS device with a low on-resistance includes: a super-junction structure disposed on a drain region; a super-junction structure having a first semiconductor pillar and a second semiconductor pillar. A HEMT structure having heterojunctions is formed between the first semiconductor pillar and the second semiconductor pillar. The HEMT structure includes a first semiconductor material pillar and a second semiconductor material pillar. Heterojunctions are formed in the super-junction structure to form the HEMT structure, inducing two-dimensional electronic gas to facilitate electrical conduction, such that the on-resistance of the VDMOS device is significantly reduced. The voltage difference between the first semiconductor pillar and the second semiconductor pillar in the super-junction structure is utilized to control a cutting-off behavior of the HEMT structure. The two-dimensional electronic gas is depleted when a high drain-source voltage difference is applied between the source region and the drain region, rendering the VDMOS device high-voltage resistant.

A LDMOS transistor and manufacturing method includes: forming an epitaxial layer on a substrate of a first doping type; forming a gate structure on an upper surface of the epitaxial layer; forming a source region of a second doping type in the epitaxial layer, the second doping type is opposite to the first doping type; forming a patterned first insulating layer on the upper surface of the epitaxial layer and the gate structure, and at least exposes part of the source region; forming a first conductive channel by using a sidewall as a mask, the first conductive channel extends from the source region to an upper surface of the substrate so as to connect the source region with the substrate; and forming a drain region of the second doping type in the epitaxial layer.

A semiconductor device having a ring-shaped cell region, a first termination region and a second termination region. The cell region includes a first base region, a source region in the first base region, first and second gate trench structures. The first base region and the source region are sandwiched by the first and second gate trench structure in a plane. The first termination region is surrounded by the ring-shaped cell region in the plane. The second termination region surrounds the ring-shaped cell region in the plane. The first termination region has a round-shaped source trench structure including a source electrode filling in a source trench with a source dielectric layer in between for insulation. The second termination region has a ring-shaped first source trench structure including a source electrode filling in a source trench with a source dielectric layer in between for insulation.

Disclosed is a trench-type MOSFET and a method for manufacturing the same. The method comprises: forming a trench in a semiconductor substrate; forming a first insulating layer and a shielding conductor in the trench; forming an opening on two sides of the shielding conductor in the trench, wherein the opening is separated from the shielding conductor by the first insulating layer; forming a gate dielectric layer and a gate conductor in the opening, wherein the trench extends from an upper surface of the semiconductor substrate into the semiconductor substrate, the first insulating layer covers a sidewall and a bottom of the trench and separates the shielding conductor from the semiconductor substrate, the gate dielectric layer at least covers a sidewall of the opening. The method simplifies the process steps of forming the trench-type MOSFET compared with the prior art, and reduces process errors.