Intel NDTM US LLC

An embodiment of a memory device may comprise a vertical channel, a first memory cell formed on the vertical channel, a first wordline coupled to the first memory cell, a second memory cell formed on the vertical channel immediately above the first memory cell, a second wordline coupled to the second memory cell, and an airgap disposed between the first wordline and the second wordline. Other embodiments are disclosed and claimed.

An embodiment of an apparatus may include NAND memory organized as two or more memory planes and a controller communicatively coupled to the NAND memory, the controller including circuitry to provide synchronous independent plane read operations for the two or more memory planes of the NAND memory. Other embodiments are disclosed and claimed.

Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.

Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.

Methods and apparatus for fast and efficient verify recovery and array discharge for 3D NAND memory arrays and other 3D storage devices. The 3D storage device includes storage arrays including strings of memory cells stacked on top of one another and sharing a channel in a pillar for the string. The memory cells for a string occupy respective tiers in a 3D structure with each tier having an associated wordline. A controller is used to program charge levels in the memory cells. Programming is followed by a fast verify recovery where a voltage is applied to the wordlines to perform a program verify, followed by discharging wordlines. Erased wordlines are identified and discharged first, followed by programmed wordlines, which may employ staggered discharge sequences. Dummy wordlines are then discharged, with an optional timer delay. For multi-deck devices, wordlines in the deck with an active wordline are discharged before wordlines in one or more other decks.

NAND performance is increased by reducing the time to perform program operations. An operation to program a portion of NAND cells in a NAND memory array includes multiple stages. NAND performance is increased by reducing the time in a first stage of the multiple stages to compute parameters that are used in a second stage to perform program operation(s) and verify operation(s). The time in the first stage is reduced by enabling dynamic prologue selection to dynamically select one of multiple sets of first stage operations to be performed in the first stage for a program operation based on the Word Line (WL), WL-Group, and block information for a current program operation and a previous program operation.

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

A ring oscillator (RO) circuit for capturing one or more characteristics relating to aging of CMOS circuitry in a CMOS device has been described. The RO circuit includes a plurality of stages coupled via an RO feedback signal line and forming an inverter chain. The plurality of stages include, for each stage, a respective CMOS inverter comprising a pair of pMOS and nMOS transistors followed by a pass gate, wherein an output of a pass gate for a stage is coupled to an input for the respective CMOS inverter of a next stage. The plurality of stages include an enable stage to enable the inverter chain to be put into a free oscillating mode or another mode in which the RO circuit does not freely oscillate. The plurality of stages include a Device Under Test (DUT) stage preceded by a pre-stage where respective supply rails of the DUT stage and pre-stage are isolated from one another.

Systems, apparatuses, and methods may provide for technology that arranges a wordline access structure for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a plurality of wordlines penetrating through a plurality of decks of a non-volatile memory structure. A plurality of through array vias penetrate through the plurality of decks, where the plurality of through array vias and the plurality of wordlines are comingled in a shared wordline access structure area. Additionally, or alternatively, the memory device is manufactured based on forming multi-level via holes penetrating through a plurality of decks of a non-volatile memory structure of a memory device based on wordline contact patterning. A metal film is deposited to fill the via holes to form wordline contacts.

Methods and apparatus for Enhanced IO Interface for PLC program and program-suspend-resume operations. A NAND memory device includes blocks of single-level cell (SLC) memory and multi-level cell (MLC) memory storing n-bits per cell such as quad-level cell (QLC) or penta-level cell (PLC) memory. The NAND memory device further includes a plurality of page buffer latches and logic to copy data from a set of n SLC pages in a block of SLC memory into n respective page buffer latches and copy data from the respective page buffer latches to an MLC page (e.g., QLC or PLC page) in a block of MLC memory. These operations can be extended for NAND memory devices having multiple planes with blocks of SLC and QLC/PLC memory. QLC/PLC program and program-resume operations are supported with optional ECC correction operations.