Sandisk Technologies, Inc.

A semiconductor device includes an ultrathin controller die. In embodiments, a semiconductor die is be mounted on a substrate. The die may be thinned by backgrinding before being mounted on the substrate. Thereafter, a protective coating is applied to the die and substrate, and the protective coating is processed to expose an upper, inactive surface of the die. The die is then thinned by a plasma etching process to partially or completely remove the inactive silicon layer of the die. Thereafter, the protective coating may be removed leaving only the ultrathin die on the substrate. In some embodiments, the die is a memory controller die.

A printed circuit board (PCB) for an electronic device assembly, such as a solid state drive (SSD), includes at least one solder mask formed from a healable dielectric material and/or conductive traces formed from a healable conductive material. Thus, the solder mask(s) and/or conductive traces may be selectively healed. The healable dielectric material may flow when heated to a repair temperature. The healable conductive material may flow upon application of a repair voltage to it. Electronic device assemblies are also disclosed, as are methods for repairing solder masks and conductive traces of the PCBs of electronic device assemblies.

An interposer includes a number of features that electrically and mechanically support a vertical mounted connector. The interposer includes multiple sets of contacts on a top surface. The contacts are arranged and/or adapted to contact respective pins of the connector when the connector is vertically mounted on the interposer. Each contact in each set of contacts is electrically coupled, using a trace, to a respective pad on the bottom surface of the interposer. The contacts, the traces, and the pads are arranged in a fan-out configuration. The interposer also includes a number of securement features that strengthen a mechanical connection between the connector and the interposer.

A non-volatile memory system performs a sensing process for memory cells by sensing the memory cells multiple times to achieve multiple results for determining whether the memory cells are in a particular condition (e.g., a memory cell current distribution) in response to a same reference signal without adjusting the memory cell between the multiple times. The memory system determines whether the memory cells are in the particular condition based on whether a majority of the multiple results indicate that the memory cells are in the particular condition. In one embodiment, the system programs weight information into the non-volatile memory cells and performs vector-matrix multiplication using the weight information programmed in the non-volatile memory cells. The sensing the memory cells multiple times to achieve multiple results can be performed as part of a program verify process when programming weight information and/or as part of the vector-matrix multiplication.

A non-volatile memory system adjusts a subset of memory cells, while reducing disturbs to memory cells inhibited from the adjustment, by applying adjustment voltages for different lengths of time based on current condition of the memory cells.

The disclosure relates in some aspects to managing power states in a data storage device. A data storage device may receive a request from a host device to transition to a particular power state. Such a request may be used to cause the data storage device to transition to a corresponding internal power state. In some scenarios, the host device might not support the same internal power states that are supported by the data storage device. In this case, the data storage device may transition to an internal power state that is lower than the internal power state supported by the host device in conjunction with the request.

A laser cutting process for ensuring a plasma plume or cloud that forms during a substrate cutting process does not lead to undesired re-deposition of material onto the substrate. At least one electrode is biased to draw the electrons of the plasma plume or cloud towards the electrode and away from the substrate. A vacuum port and/or a blower may be strategically located to ensure gas flow away from the substrate and hence, directing of the electrons away from the substrate. In so doing, material re-deposition is less likely to occur.

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located on a semiconductor layer, a memory opening vertically extending through the alternating stack and the semiconductor layer, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and a source layer that is formed at the bottom end of a vertical semiconductor channel. The source layer may comprise at least one metal that provides a Schottky contact to the vertical semiconductor channel.

Servers, methods, and computer-readable media for performing thermal management of a server including a plurality of data storage devices. In one example, a server includes a controller configured to apply a machine learning model to identify a first portion of the plurality of data storage devices located in a hot zone relative to a second portion of the plurality of data storage devices located outside of the hot zone. The controller identifies the hot zone based on thermal data received from each of the plurality of data storage devices. Based on an identification of the first portion of the plurality of data storage devices located in the hot zone, the controller performs thermal management of the plurality of data storage devices by logically shuffling the plurality of data storage devices to create a distributed hot zone.

In the context of an electronic storage device such as a solid-state drive, a heat-mitigating enclosure includes one or more thermal conduction inhibitor interposed in the respective top or bottom enclosing structure and positioned between a relatively high-temperature electronic component such as an ASIC controller and/or PMIC of a corresponding PCB and a relatively low-temperature electronic component such as NAND memory. Such a thermal conduction inhibitor may include one or more through-hole through the enclosure structure and/or a recess extending into the enclosure structure, with or without a low thermal conductivity material embedded therein.