Silanna UV Technologies Pte Ltd

The techniques described herein relate to a method for generating a binary-oxide vapor precursor for a deposition process including: providing a binary-oxide vapor source; heating the binary-oxide vapor source to form an elemental vapor from an elemental component contained therein; and reacting the elemental vapor with solid binary-oxide members contained therein. The binary-oxide vapor source can include: a closed end and an open end; a first region located adjacent to the closed end including the elemental component; and a second region located between the first region and the open end, the second region including a contained aggregate structure including the solid binary-oxide members and spaces through which a vapor can pass. In some aspects, the techniques described herein relate to a material deposition system including the binary-oxide vapor source coupled to a growth chamber.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a gate oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

The techniques described herein relate to a transistor including a substrate including sapphire, an epitaxial channel layer on the substrate, and an epitaxial gate layer on the channel layer. The epitaxial channel layer can include α-Ga 2 O 3 , with a first bandgap. The epitaxial gate layer can include an oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap. The transistor can also include electrical contacts, including: a source electrical contact coupled to the epitaxial channel layer; a drain electrical contact coupled to the epitaxial channel layer; and a gate electrical contact coupled to the epitaxial gate layer.

A multilayered semiconductor diode device can include a substrate including silicon carbide (SiC) with an epitaxial drift layer including a first semiconductor oxide material above the SiC substrate with respect to a growth direction. The multilayered semiconductor diode device can further include a polar nitride layer including a polar semiconductor nitride material above the epitaxial drift layer with respect to the growth direction, and a metal layer above the polar nitride layer with respect to the growth direction.

The techniques described herein relate to a transistor, including a substrate, an epitaxial buffer layer, an epitaxial channel layer, and a gate layer. The substrate includes a first oxide material with a first crystal symmetry, the epitaxial buffer layer includes a second oxide material with a second crystal symmetry, the epitaxial channel layer includes a third oxide material with a third crystal symmetry and a first bandgap, and the gate layer includes a fourth oxide material with a second bandgap. The first crystal symmetry is different from either the second crystal symmetry or the third crystal symmetry, and the second bandgap is wider than the first bandgap. The transistor also includes electrical contacts including a source electrical contact coupled to the epitaxial channel layer, a drain electrical contact coupled to the epitaxial channel layer, and a gate electrical contact coupled to the gate layer.

The techniques described herein relate to a transistor including a single crystal substrate, an epitaxial channel layer (ECL) on the single crystal substrate, a gate layer on the ECL, a source electrical contact coupled to the ECL, a drain electrical contact coupled to the ECL, and a gate electrical contact coupled to the gate layer. The substrate includes a substrate material with a first crystal symmetry and the ECL includes an ECL oxide material with a second crystal symmetry, where the first crystal symmetry is different from the second crystal symmetry. The gate layer includes a gate oxide material, where the ECL oxide material has a first bandgap and the gate oxide material has a second bandgap, and the second bandgap is wider than the first bandgap.

A multilayered semiconductor diode device can include a substrate including silicon carbide (SiC) with an epitaxial drift layer including a first semiconductor oxide material above the SiC substrate with respect to a growth direction. The multilayered semiconductor diode device can further include a polar nitride layer including a polar semiconductor nitride material above the epitaxial drift layer with respect to the growth direction, and a metal layer above the polar nitride layer with respect to the growth direction.

In some embodiments, a semiconductor structure includes a single crystal substrate, a first epitaxial oxide layer on the single crystal substrate, and a second epitaxial oxide layer on the single crystal substrate. The first epitaxial oxide layer can include a first oxide material with a cubic crystal symmetry. The second epitaxial oxide layer can include a second oxide material with a monoclinic crystal symmetry. The second epitaxial oxide layer can be elastically strained to the first epitaxial oxide layer. The substrate can include MgO, MgAl 2 O 4 , or β-Ga 2 O 3 . The first epitaxial oxide layer can include MgO with a cubic crystal symmetry oriented in the (100) direction, and the second epitaxial oxide layer can include β-Ga 2 O 3 oriented in the (100) direction, where there is a 45° rotation around the (100) direction between the MgO and the β-Ga 2 O 3 crystal structures.

Methods and systems of heating a substrate in a vacuum deposition process include a resistive heater having a resistive heating element. Radiative heat emitted from the resistive heating element has a wavelength in a mid-infrared band from 5 μm to 40 μm that corresponds to a phonon absorption band of the substrate. The substrate comprises a wide bandgap semiconducting material and has an uncoated surface and a deposition surface opposite the uncoated surface. The resistive heater and the substrate are positioned in a vacuum deposition chamber. The uncoated surface of the substrate is spaced apart from and faces the resistive heater.

Various forms of Mg a (Si x (Ge y Sn 1-y ) 1-x )O b are disclosed. In some aspects, an epitaxial layer comprises single crystal Mg a (Si x (Ge y Sn 1-y ) 1-x )O b , wherein 1.5≤a≤2.5, 3≤b≤5, 0≤x≤1, and 0≤y≤1; wherein the single crystal Mg a (Si x (Ge y Sn 1-y ) 1-x )O b has a crystal symmetry compatible with a substrate or an underlying layer on which the single crystal Mg a (Si x (Ge y Sn 1-y ) 1-x )O b is grown. In some aspects, a semiconductor structure includes an epitaxial layer comprising single crystal Mg a (Si x (Ge y Sn 1-y ) 1-x )O b , wherein 1.5≤a≤2.5, 3≤b≤5, 0≤x≤1, and 0≤y≤1; The semiconductor structure also includes a substrate or an underlying layer on which the single crystal Mg a (Si x (Ge y Sn 1-y ) 1-x )O b is grown; wherein the single crystal Mg a (Si x (Ge y Sn 1-y ) 1-x )O b has a crystal symmetry compatible with the substrate or the underlying layer.