WALTON ADVANCED ENGINEERING, INC.

A semiconductor memory packaging unit is provided. The semiconductor memory packaging unit includes a chip package, a plurality of first connecting bodies, and a substrate. The chip package is further provided with a redistribution layer (RDL) composed of a dielectric layer and a plurality of conductive circuits. The conductive circuits are electrically connected to a plurality of die pads on a chip of the chip package. A circuit layout space on the die pads of the chip package is improved by the RDL. Thereby a layout of pads for connecting the conductive circuit with the outside can be adjusted. Therefore, the layout of circuits is easy for manufacturers to prevent the circuits from too dense and this helps reduction of production cost and improves reliability and yield rate of products.

A fan-out wafer-level packaging (FOWLP) unit which includes a substrate, at least two dies, a first dielectric layer, a second dielectric layer, conductive circuits, and an outer protective layer is provided. The conductive circuits are formed by a metal paste filled in first slots of the first dielectric layer and second slots of the second dielectric layer. One end of the conductive circuit is electrically connected to a die pad of the die while the other end is exposed through an opening of the outer protective layer and formed a bonding pad in the opening. At least one of the bonding pads is located around a chip area on a second surface of the die. The dies are electrically connected to the outside through the die pads, the conductive circuits, and the bonding pads. Thereby problems including higher manufacturing cost and less environmental benefit can be solved.

A fan-out wafer level packaging (FOWLP) unit which includes a substrate, a die, a first dielectric layer, a second dielectric layer, a plurality of conductive circuits, and an outer protective layer is provided. The conductive circuit is formed by metal paste filled in a plurality of first slots at the first dielectric layer and a plurality of second slots on the second dielectric layer. One end of the conductive circuit is electrically connected with a plurality of die pads of the die while the other end forms a bonding pad in respective openings of the outer protective layer and the bonding pad is exposed. At least one of the bonding pads is located around a chip area on a second surface of the die to form the FOWLP unit. The die is electrically connected to the outside through the die pads, the conductive circuits, and the bonding pads.

A chip package with at least one electromagnetic interference (EMI) shielding layer and at least one ground wire and a method of manufacturing the same are provided. The chip package includes a chip package unit, at least one EMI shielding layer, and at least one ground wire. The ground wire which consists of a first end and a second end opposite to the first end is inserted through the EMI shielding layer and a first insulating layer of the chip package unit. The first end is electrically connected with the EMI shielding layer while the second end of the ground wire is electrically connected with at least one grounding end of at least one first circuit layer of the chip package unit for protection against static electricity. Thereby malfunction of an electronic system with semiconductor chips due to static electricity can be avoided.

A chip package with redistribution circuits is provided. The chip package includes a chip, a plurality of redistribution circuits, and a plurality of nickel immersion gold layers. The redistribution circuits are formed and horizontally extending on the surface of the chip by a redistribution layer (RDL) process. The nickel immersion gold layer is plated on a surface of the redistribution circuit by an electroless nickel immersion gold (ENIG) process. Each of the nickel immersion gold layers is formed by a nickel layer and a gold layer located over the nickel layer. Thereby problems of the chip package available now including uneven thickness of the nickel immersion gold layer caused by electroplating process and the complex manufacturing process can be solved. The design space and reliability of the chip package are effectively improved by the RDL process.

A chip packaging unit with dual redistribution layers (RDL) and a method of manufacturing the same are provided. The chip packaging unit includes a chip, a first RDL disposed on a first surface of the chip, a second RDL arranged at a second surface of the chip, and at least one lateral surface connecting circuit. The chip is electrically connected to a plurality of external connection bodies on second conductive circuits through a plurality of die pads on the chip, a plurality of first conductive circuits of the first RDL, the lateral surface connecting circuits, and the second conductive circuits of the second RDL in turn. Then the chip is electrically connected to the outside through the external connection bodies. Thereby problems including complicated structure with larger thickness caused by arrangement of multiple layers of circuits or through silicon via can be solved and production cost is reduced.

A chip package having four sides provided with electromagnetic interference (EMI) shielding layers correspondingly and a method of manufacturing the same are provided. The four EMI shielding layers are made of metals, located on four lateral sides of the chip package, and completely covering four lateral sides of a substrate and four lateral sides of an insulating layer to prevent at least one first circuit layer, at least one second circuit layer, and at least one chip from electromagnetic interference. Moreover, the EMI shielding layers help to improve heat dissipation efficiency of the first circuit layer, the second circuit layer, and the chip.

A chip package having die pads with protective layers is provided. At least one protective layer is covering and arranged at a peripheral zone of at least one die pad for minimizing area of the die pad exposed outside as well as shielding and protecting the peripheral zone of the die pad. A weld zone of the die pad is not covered by the protective layer so that the weld zone of the die pad is exposed. In a crossed-over state, one of bonding wires crossing one of the die pads with a corresponding connection pad of a carrier plate will not get across a second upper space defined by the weld zone of the rest of the die pads. Thereby the one of the bonding wires can be more isolated by the protective layers on the peripheral zones of the rest of the die pads.

A chip package with electromagnetic interference (EMI) shielding layer and a method of manufacturing the same are provided. The chip package includes a chip, a redistribution layer (RDL), an insulating layer, and an electromagnetic interference (EMI) shielding layer. A peripheral wall is formed around at least one first opening of the insulating layer for enclosing the first opening and a flat portion is disposed around the peripheral wall while a level of the flat portion is lower than a level of the peripheral wall. The flat portion of the insulating layer is covered with the EMI shielding layer which is isolated and electrically insulated from a pad in the first opening by the peripheral wall of the insulating layer. Thereby problems of the chip including fast increase in temperature and electromagnetic interference can be solved effectively.

A fan-out wafer level packaging (FOWLP) unit and a package formed by stacking the same are provided. The FOWLP unit includes a substrate, at least one die, a first dielectric layer, at least one second conductive pillar, a second dielectric layer, a plurality of first conductive circuits, a third dielectric layer, and a plurality of metal protective layers. The first conductive circuits are produced on a second surface of the die by filling a metal paste into slots and grinding the metal paste. A layout of second bonding pads on a first surface of the FOWLP unit and a layout of first bonding pads on a second surface of the FOWLP unit are the same and this is beneficial to mass-production of the FOWLP units.