Company patents
WALTON ADVANCED ENGINEERING, INC.
WALTON ADVANCED ENGINEERING, INC. exhibits a strong, albeit consolidating, focus on semiconductor technologies, with Chip-to-Chip Interconnect (Bonding, Bumps) and Semiconductor Packaging & Encapsulation together representing 100% of its portfolio in 2026 so far, despite both categories showing a decline in patent filings from 2025 (YoY -28.6% and -25.0% respectively). Surprisingly, while core semiconductor areas are seeing a slowdown, the company shows an emerging focus in Printed Circuits & Electronic Assemblies, with a 100.0% YoY growth in 2026 (2 patents so far), suggesting a strategic shift towards broader electronic assembly innovations.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
50 US filings (since 2023) · 12 categories · 14 themes
Methods and structures for integrating and enclosing electronic components into compact, multi-functional modules, often involving embedded components, multi-layer substrates, and electromagnetic shielding for performance and miniaturization.
Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.
Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.
Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.
Technologies for establishing and maintaining secure communication channels between devices or networks, often employing encryption, secure protocols, or virtual private networks (VPNs).
Inspection and testing methods specifically designed for wafers before, during, or after bonding processes, including verification of bonding surfaces, alignment, and defect detection in multi-wafer or stacked die assemblies.
Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.
Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.
Materials and processes for hermetic encapsulation, conformal coating, optical chip sealing, and stretchable conductors for electronic and optoelectronic devices.
Methods and systems for enhancing the security and privacy of electronic messages, often by integrating contextual data such as location, social network graphs, or user authentication levels to control access, filter content, or enable specific group interactions.
Patents
Showing 1-10 of 10
Heterogeneous Chiplet Integration