WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.

A pixel circuit and an image sensor are disclosed. The pixel circuit has a photodiode and at least three MOS transistors. The at least three MOS transistors include a first transistor, a second transistor, and a third transistor, wherein a cathode of the photodiode is connected to a first terminal of the first transistor, and a second terminal of the first transistor is connected to a first terminal of the second transistor and a gate of the third transistor, wherein a threshold voltage of the first transistor is higher than a threshold voltage of the second transistor, and an off-state leakage current under operating voltage of the first transistor is less than an off-state leakage current under operating voltage of the second transistor.

The present invention relates to a vertically-charge-transferring pixel sensor (VPS) and methods of manufacture and operation thereof. In the VPS, deep trench isolation (DTI) structures and shallow trench isolation (STI) structures in a substrate contain deep trench electrodes and shallow trench electrodes, respectively. In a light sensing operation, a positive bias voltage can be applied between the substrate and the deep and shallow trench electrodes to raise a potential barrier at boundaries of the DTI and STI structures and the substrate. This reduces the likelihood of photoelectrons being captured at the boundaries, thus reducing loss of photoelectrons and contributing to enhanced quantum efficiency. In addition, in the STI structures, the shallow trench electrodes may be offset toward light sensing regions beside the STI structures. In this way, a voltage applied to the shallow trench electrodes has a greater impact on potentials in the light sensing regions than on potentials in charge readout regions, thus additionally reducing loss of photoelectrons and minimizing the influence on MOS transistors in the charge readout regions.

A semiconductor structure and a method for fabricating it are disclosed. In the semiconductor structure, a heat-equalizing layer is arranged between stacked first and second substrates and includes a heat-dissipating material film, which can promote horizontal transfer of heat produced in the semiconductor structure between the first and second substrates.

A bonding method, a wafer stacking structure, and a chip structure are provided. The bonding method includes: providing at least one first wafer stacking structure, and testing each chip region of the first wafer stacking structure, the first wafer stacking structure includes at least two first wafers bonded together; dicing the first wafer stacking structure to form chips, each of the chips corresponding to a corresponding one chip region; and bonding a chip with good functions, which corresponds to a corresponding chip region with good functions determined in the operation of testing each chip region of the first wafer stacking structure, to a second wafer.

Disclosed in the present disclosure are a semiconductor device and manufacturing method thereof. The method comprises: bonding the front surface of a top wafer to the front surface of a first wafer, and enabling the front surface of the top wafer to face upwards and the front surface of the first wafer to face downwards; bonding the front surface of a second wafer to the back surface of the first wafer to form a bonding structure, and enabling the front surface of the second wafer to face downwards; flipping the bonding structure to enable the front surface of the first wafer and the front surface of the second wafer to face upwards, and forming a pad pin in a top chip substrate.

A manufacturing method for a memory device, a memory device, and a memory cell. The manufacturing method includes: providing a semiconductor substrate, which includes a substrate and a hard mask layer; defining first trenches in the substrate, some of which are located in a memory region and others are located in a lead-out region; forming a gate insulating layer and a semi-floating gate on a bottom of each base trench, where a portion of the semi-floating gate contacts the substrate, and another portion is isolated from the substrate; and forming an inter-gate dielectric layer and a first gate layer in each first trench, removing a portion of the first gate layer in each first trench in the memory region to form a control gate, and retaining the first gate layer in each first trenches in the lead-out region as a lead-out line.

The application provides a manufacturing method for a memory device, and a memory device. The manufacturing method includes: providing a semiconductor base including a substrate and a first trench; forming a gate insulating layer and a first gate material layer; removing a part of the first gate material layer and a part of the gate insulating layer to form a contact window, and forming a second gate on the contact window, the second gate contacting the substrate and having a continuous lattice structure with the substrate; forming an island structure covering the first trench, a portion of the first gate material layer remaining in the island structure serving as a first gate, the first gate contacting the second gate, and the first gate and the second gate constituting a semi-floating gate of a memory cell in the memory device.

The present application provides a memory block and a manufacturing method therefor, and a memory cell. The method includes: providing a semiconductor substrate; forming a plurality of word-line holes on the semiconductor substrate to divide each memory subarray layer into a plurality of columns of drain region semiconductor strips, channel semiconductor strips, and source region semiconductor strips; forming a floating gate storage structure on at least one side of a part of each word-line hole that exposes corresponding channel semiconductor strips; and filling a gate material in each word-line hole to form a plurality of gate strips. A part of the gate strip, a corresponding part of the channel semiconductor strip, a part of the floating gate storage structure interposed between thereof, and a part of the drain region semiconductor strip and a part of the source region semiconductor strip are configured to form a memory cell.

A method of handling a test pad and a method of fabricating a semiconductor device are disclosed. The method of handling a test pad includes: providing a substrate formed thereon with a first insulating dielectric layer and a first test pad in the first insulating dielectric layer, wherein a surface of the first test pad is at least partially exposed from the first insulating dielectric layer, and there is a probe mark with a protrusion resulting from testing with probe tips on the surface portion of the first test pad exposed from the first insulating dielectric layer; and heating and melting the protrusion by laser annealing, thereby reducing a height of the protrusion. This invention can ensure good flatness of a surface to be bonded while enabling reduced process complexity and preventing metal contamination of the surface to be bonded.

A method for fabricating an interposer structure includes: providing a substrate; forming a first opening and filling a first conductive layer in the first opening; forming a first dielectric layer on a first surface of the substrate and forming a first redistribution metal layer in the first dielectric layer; forming a second opening and filling a second conductive layer in the second opening; forming a second dielectric layer on a second surface of the substrate and forming a second redistribution metal layer in the second dielectric layer. Through the redistribution metal layer for wiring is formed on both sides of the substrate in the thickness direction, the high-intensity interconnection requirements can be satisfied. The first opening and the second opening are formed from both sides of the substrate in the thickness direction, respectively, and communicate with each other to make up a TSV hole.