Company patents
WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD. shows a surprising shift in its patent strategy, moving away from its largest category, Semiconductor Manufacturing Process (30.1% of portfolio), which has seen consistent declines, including a -12.5% YoY drop in 2026 so far, and a dramatic -100.0% YoY decline in Integrated Circuit Layout & Arrangement. Concurrently, the company is rapidly emerging in new areas, with Photovoltaic / Photoconductive Devices experiencing a +166.7% YoY growth and Semiconductor Diodes & Transistors seeing a remarkable +350.0% YoY growth in 2026, indicating a strategic pivot towards these high-growth sectors.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
136 US filings (since 2023) · 12 categories · 27 themes
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Techniques and methodologies for fabricating semiconductor devices, including etching, deposition, annealing, isolation, and doping steps, aimed at improving yield, performance, or enabling new structures.
Inspection and testing methods specifically designed for wafers before, during, or after bonding processes, including verification of bonding surfaces, alignment, and defect detection in multi-wafer or stacked die assemblies.
Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.
Focuses on advanced pixel architectures, often involving vertical stacking (3D) or silicon-on-insulator (SOI) structures, to improve performance, density, or functionality of photodiodes, transistors, and floating diffusion regions within image sensor pixels.
Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.
Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.
Techniques for designing and fabricating the conductive pathways (interconnects) and their contacts between different components within an integrated circuit, focusing on density, reliability, and performance.
Layout, material composition, and structural arrangement of photoelectric conversion elements and associated circuitry within image sensor arrays, including infrared detectors and back-side illuminated structures.
Methods and circuits for detecting and mitigating defects, ensuring data integrity, and enabling self-testing and repair mechanisms within memory devices and subsystems.
Techniques for forming electrical contacts, vias, and interconnects to semiconductor devices, including advanced methods like contact-over-active-gate (COAG) and backside contacts for improved density and performance.
Integration of various sensor types (e.g., thermal, strain) or display components directly onto semiconductor substrates or within device architectures for compact and high-performance systems.
Image sensors tailored for specific advanced functionalities beyond basic image capture, such as high dynamic range (HDR) imaging, single-photon detection, auto-focus, or distance measurement (LiDAR), often incorporating specialized pixel designs or processing.
Design and implementation of non-traditional logic gates or memory elements, often leveraging new materials or device physics to achieve multi-functionality, adaptive thresholds, or higher density.
Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.
Focuses on novel semiconductor materials, heterostructures, and doping profiles to improve photovoltaic conversion efficiency, stability, and spectral response.
The design and manufacturing of integrated circuits that combine optical and electronic components, particularly for high-speed data communication between processors and memory.
Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.
Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.
Focuses on the design and manufacturing of transistors where the gate material fully encircles the channel, often using nanosheets or fins, to improve electrostatic control and reduce short-channel effects.
Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.
Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.
Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.
Physical layout and material composition of individual pixels within a display panel, including active layers, electrodes, light-emitting elements (LEDs, OLEDs), and associated thin-film transistors (TFTs).
Integration of dedicated physical structures or built-in circuitry within semiconductor devices to enable characterization of process variations, material properties, electrical leakage, or device performance.
Patents
Showing 1-10 of 22
Memory System Performance & Reliability