CXMT Corporation

A semiconductor structure includes at least one sub-word line driver. The sub-word line driver includes a plurality of first active areas and a main-word line. The main-word line includes a plurality of first gates and a plurality of second gates interconnected. The plurality of first gates correspond to the plurality of first active areas. An extension direction of the plurality of first gates in the main-word line and/or an extension direction of at least part of the second gates in the main-word line intersects both a first direction and a second direction. The first direction is parallel to a direction in which the first active areas extend, and the second direction is parallel to a plane in which the first active areas are located and is perpendicular to the first direction.

A semiconductor structure includes: an interposer, wherein the interposer has a trench array including multiple trenches extending from a top surface of the interposer toward an interior of the interposer, the multiple trenches further extend in a preset direction parallel to the top surface of the interposer; a capacitor located in the trenches, wherein the capacitor includes a first electrode layer, a first capacitor dielectric layer, and a second electrode layer being sequentially stacked, the first capacitor dielectric layer covers a surface of the first electrode layer, and the second electrode layer covers a surface of the first capacitor dielectric layer; lead-out electrode layers located in the interposer, wherein the lead-out electrode layers are electrically connected to the first electrode layer and/or the second electrode layer and extend in the preset direction. The semiconductor structure has the advantages of large capacity, fast charge and discharge, high integration, and high reliability.

An integrated circuit package, including: a memory chip and a logic chip; and an interface connection structure. The interface connection structure includes a physical layer and conductive pillars connected to the physical layer, the physical layer includes a first physical layer, a second physical layer, and a logical connection layer, the first physical layer is a physical layer of the memory chip, the second physical layer is a physical layer of the logic chip, and both the first physical layer and the second physical layer are connected to the logical connection layer.

Provided a broadcast circuit for a fuse array, a broadcast method for a fuse array, and a memory apparatus. The broadcast circuit for the fuse array includes: a broadcast address detector, configured to receive a broadcast fuse address count to generate N enable signals; and N sub-broadcast circuits, each includes: a gating circuit, connected to the fuse array and the broadcast address detector, and configured to: receive one of the enable signals, a broadcast clock signal, and broadcast data, and output a gated broadcast clock signal and gated broadcast data when the enable signal is valid; and a broadcast bus and a latch circuit, where the broadcast bus is connected to the gating circuit and the latch circuit, and the broadcast bus is configured to transmit the gated broadcast clock signal and the gated broadcast data to the latch circuit.

A soft repair control circuit includes a lock control circuit, an undo control circuit, a soft repair address latch circuit, and a soft repair address matching circuit. The lock control circuit locks an output latch control signal into a first level when a lock enable signal is at an active level. The undo control circuit maintains an output unchanged and the soft repair address latch circuit maintains an output unchanged when the latch control signal is locked into the first level and generates an undo flag signal at an active level according to an undo enable signal at an active level when the latch control signal is an inverted delayed signal of a soft repair pulse signal. The soft repair address matching circuit locks an output soft repair matching signal into an inactive level when the undo flag signal is at an active level.

A repair method and circuit for a memory is provided. The repair method includes the steps as follows: the memory receives a repair instruction sent from the outside, where the repair instruction carries a failed address, and the failed address is a memory cell address of a failed memory cell. A fuse array is broadcast and whether a currently broadcast fuse address is a target fuse address is sequentially determined, until at least one target fuse address is found, where the target fuse address is a fuse address mapped to a target redundant address, and the target redundant address is a redundant address capable of repairing the failed address. The failed address is written into the first unused target fuse address in the at least one target fuse address, to access the target redundant address when a request for accessing the failed address is received.

Embodiments of the present application relate to the field of memories and provide a memory. The memory includes a first chip, a second chip, a third chip, and a fourth chip stacked in sequence along a first direction, where a logic circuit is formed on the first chip, a first memory array is formed on the second chip, a core region circuit is formed on the third chip, and a second memory array is formed on the fourth chip.

A three-dimensional semiconductor device and a manufacturing method therefor. The three-dimensional semiconductor device includes multiple semiconductor layers, multiple word lines, multiple bit lines, and multiple memory nodes. The multiple word lines are arranged at intervals in the vertical direction, and each include one pair of traces respectively located on two opposite surfaces of each of the semiconductor layers in the vertical direction. The traces include first portions and second portions that are arranged alternately. The size of the first portion is greater than the size of the second portion in the second horizontal direction. The bit lines extend in the vertical direction and are coupled to one end of each of the multiple semiconductor layers in the vertical direction. The three-dimensional semiconductor device can at least improve a current driving capability of a transistor, and reduce mutual interference between adjacent memory cells.

An internal error-checking circuit includes a clock generation circuit, an internal command generation circuit, an address generation circuit, a control logic circuit, and an error correction circuit. The clock generation circuit generates and outputs a self-refresh clock signal in response to a self-refresh enable signal; the internal command generation circuit counts the self-refresh clock signals when the error-checking enable signal indicates that an internal error-checking function is enabled and generates and outputs one internal error-checking command signal when the count value of the self-refresh clock signal is a first preset value; the address generation circuit counts the internal error-checking command signal to generate and output an internal error-checking address; the control logic circuit controls, in response to the internal error-checking command signal, the error correction circuit to sequentially execute a single internal read-modify-write operation on the target memory cells corresponding to the internal error-checking address in memory arrays.

Provided is a method for manufacturing a trench capacitor. The method includes the steps as follows. A substrate is provided, where the substrate has a first trench. A first electrode layer is formed in the first trench, where the first electrode layer covers the first trench and a surface of the substrate. A first dielectric layer is formed, where the first dielectric layer covers the first electrode layer. A second dielectric layer is formed, where the second dielectric layer covers at least the first dielectric layer on the surface of the substrate, and the second dielectric layer has a thickness greater than that of the first dielectric layer. A second electrode layer is formed on the second dielectric layer, where the second electrode layer covers the second dielectric layer. A third dielectric layer is formed, where the third dielectric layer fills the remaining first trench.