CXMT Corporation

A semiconductor structure includes: an interposer, wherein the interposer has a trench array including multiple trenches extending from a top surface of the interposer toward an interior of the interposer, the multiple trenches further extend in a preset direction parallel to the top surface of the interposer; a capacitor located in the trenches, wherein the capacitor includes a first electrode layer, a first capacitor dielectric layer, and a second electrode layer being sequentially stacked, the first capacitor dielectric layer covers a surface of the first electrode layer, and the second electrode layer covers a surface of the first capacitor dielectric layer; lead-out electrode layers located in the interposer, wherein the lead-out electrode layers are electrically connected to the first electrode layer and/or the second electrode layer and extend in the preset direction. The semiconductor structure has the advantages of large capacity, fast charge and discharge, high integration, and high reliability.

Provided is a method for manufacturing a trench capacitor. The method includes the steps as follows. A substrate is provided, where the substrate has a first trench. A first electrode layer is formed in the first trench, where the first electrode layer covers the first trench and a surface of the substrate. A first dielectric layer is formed, where the first dielectric layer covers the first electrode layer. A second dielectric layer is formed, where the second dielectric layer covers at least the first dielectric layer on the surface of the substrate, and the second dielectric layer has a thickness greater than that of the first dielectric layer. A second electrode layer is formed on the second dielectric layer, where the second electrode layer covers the second dielectric layer. A third dielectric layer is formed, where the third dielectric layer fills the remaining first trench.

A semiconductor structure includes: an interposer and a capacitor. The interposer has holes and trenches extending from a top surface of the interposer toward an inside of the interposer. The capacitor located in the holes and the trenches includes a first electrode layer, a capacitor dielectric layer, and a second electrode layer which are sequentially stacked; the capacitor dielectric layer covers a surface of the first electrode layer, the second electrode layer covers a surface of the capacitor dielectric layer. The trenches extend in a direction parallel to the top surface of the interposer and communicate with a plurality of holes spaced apart in the direction, a width dimension of the holes is larger than a width dimension of the trenches. The semiconductor structure has the advantages of large capacity, rapid charge and discharge, and high integration, and the layout of the semiconductor structure can better solve the stress problem.

Disclosed a method includes a base substrate, bit line structures and first openings. A first initial material layer covers the bit line structures. A first material layer, the thickness of the first material layer increases from the top of the bit line structure to a first position at a first rate and increases from the first position to the bottom of the first material layer at a second rate. A second material layer covers the first material layer. A first initial dielectric layer fills portions of the first openings; part of the first initial dielectric layer is removed to form second openings and first dielectric layers. A second dielectric layer fills the second openings. The first dielectric layers are removed to form third openings. The first material layer and the second material layer above the first position are removed, and node contact holes are formed.

The present disclosure a semiconductor device, includes: a plurality of active regions disposed in a first region, each active region including a first connection terminal and a second connection terminal; a plurality of first capacitors disposed in the first region, where each first capacitor includes a first upper electrode and a first lower electrode; a plurality of second capacitors disposed in a second region, each second capacitor including a second upper electrode and a second lower electrode; a plurality of first bonding pads disposed in the first region, at least one first bonding pad being connected to the second connection terminal of at least one active region; and a plurality of second bonding pads disposed in the second region, at least one second bonding pad being connected to the second lower electrode of at least one second capacitor.

The forming method for a semiconductor structure includes following operations. A substrate is provided. The substrate includes a memory region and a boundary region sequentially adjacent to each other. An initial conductive layer is formed on the substrate and is patterned to form multiple initial bit line structures and an initial bit line contact layer. An etching mask provided with multiple first openings is formed. The initial bit line structures and the initial bit line contact layer are patterned by employing the etching mask to form multiple bit line structures and multiple bit line contact pads. Bit line isolation structures are formed. Each bit line isolation structure includes a first isolation portion located between the bit line structures and a second isolation portion located between the bit line contact pads. A first width of the first isolation portion is greater than a second width of the second isolation portion.

Disclosed a semiconductor structure includes: a substrate, including a device layer, a buried power rail, and a through silicon via, where the through silicon via is connected to the device layer through the buried power rail; a power network layer, disposed on the substrate, where the power network layer includes at least one layer of a first power array and at least one layer of a second power array, and each of the at least one layer of the first power array is connected to the buried power rail through the through silicon via; and a capacitor structure, disposed between each of the at least one layer of the first power array and each of the at least one layer of the second power array and connected to the first power array and the second power array through a lower electrode and an upper electrode of the capacitor structure respectively.

Disclosed a semiconductor structure includes: a substrate; bit line structures, located on the substrate, multiple bit line structures extending in a first direction and being disposed at intervals in a second direction; first dielectric layers, each of the first dielectric layers being located between adjacent ones of the bit line structures, and the first dielectric layers being disposed at intervals in the first direction; contact structures, each of the contact structures being located between adjacent ones of the bit line structures, and the contact structures and the first dielectric layers being alternately disposed; and conductive structures, located above the contact structures, the tops of the conductive structures being flush with the tops of the first dielectric layers; the contact structures being gradually decreased in size from the tops of the contact structures to a surface of the substrate in a direction perpendicular to the substrate.

The method includes: providing an initial structure including a plurality of dielectric layers and a plurality of conductive layers, where each of the plurality of conductive layers includes a plurality of conductive strips, a plurality of first holes penetrate through the plurality of conductive strips along a first direction; laterally thinning the plurality of conductive strips to form a plurality of first trenches; forming a plurality of first indium gallium zinc oxides in the plurality of first trenches; laterally thinning the plurality of dielectric layers to expose part of the plurality of first indium gallium zinc oxides; forming a plurality of second indium gallium zinc oxides on the surfaces of the plurality of exposed first indium gallium zinc oxides, where the concentration of indium in the plurality of first indium gallium zinc oxides is higher than that of indium in the plurality of second indium gallium zinc oxides.

The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure at least includes: an underlying conductive layer and a blocking portion, a plane in which the blocking portion is located being located above a plane in which the underlying conductive layer is located, and projections of the blocking portion and the underlying conductive layer in the vertical direction having an overlapping region; a three-dimensional structure, the three-dimensional structure including a first portion and a second portion, a top surface of the blocking portion being higher than a bottom surface of the second portion and being lower than or flush with a bottom surface of the first portion, and at least a part of the first portion being located directly above the overlapping region; a contact hole and a first conductive layer, a plane in which the first conductive layer is located being higher than a top surface of the three-dimensional structure, the contact hole being directly connected to the first conductive layer, the underlying conductive layer being electrically connected to the first conductive layer through the contact hole, and the contact hole being located on a side of the first portion away from the second portion; and a first isolation layer, the first isolation layer being configured to fill a region between the contact hole and the three-dimensional structure and a region between different contact holes.