CXMT Corporation

A soft repair control circuit includes a lock control circuit, an undo control circuit, a soft repair address latch circuit, and a soft repair address matching circuit. The lock control circuit locks an output latch control signal into a first level when a lock enable signal is at an active level. The undo control circuit maintains an output unchanged and the soft repair address latch circuit maintains an output unchanged when the latch control signal is locked into the first level and generates an undo flag signal at an active level according to an undo enable signal at an active level when the latch control signal is an inverted delayed signal of a soft repair pulse signal. The soft repair address matching circuit locks an output soft repair matching signal into an inactive level when the undo flag signal is at an active level.

A repair method and circuit for a memory is provided. The repair method includes the steps as follows: the memory receives a repair instruction sent from the outside, where the repair instruction carries a failed address, and the failed address is a memory cell address of a failed memory cell. A fuse array is broadcast and whether a currently broadcast fuse address is a target fuse address is sequentially determined, until at least one target fuse address is found, where the target fuse address is a fuse address mapped to a target redundant address, and the target redundant address is a redundant address capable of repairing the failed address. The failed address is written into the first unused target fuse address in the at least one target fuse address, to access the target redundant address when a request for accessing the failed address is received.

An internal error-checking circuit includes a clock generation circuit, an internal command generation circuit, an address generation circuit, a control logic circuit, and an error correction circuit. The clock generation circuit generates and outputs a self-refresh clock signal in response to a self-refresh enable signal; the internal command generation circuit counts the self-refresh clock signals when the error-checking enable signal indicates that an internal error-checking function is enabled and generates and outputs one internal error-checking command signal when the count value of the self-refresh clock signal is a first preset value; the address generation circuit counts the internal error-checking command signal to generate and output an internal error-checking address; the control logic circuit controls, in response to the internal error-checking command signal, the error correction circuit to sequentially execute a single internal read-modify-write operation on the target memory cells corresponding to the internal error-checking address in memory arrays.

A memory includes multiple banks, multiple error checking circuits, and an error address generation circuit. Each of the banks includes multiple data memory array tiles and an ECC memory array tile. Each of the error checking circuits is configured to separately read stored data and check data from the bank, and generate a corresponding error checking signal based on the stored data and the check data. The error address generation circuit is configured to receive multiple error checking signals from the multiple error checking circuits, and when any one of the error checking signals is at an inactive level, store address information corresponding to an error failing to meet a condition.

A memory includes: multiple data storage blocks and a check code storage block; and a data check circuit, configured to: respectively obtain stored data and a corresponding first check code from the multiple data storage blocks and the check code storage block, and determine, in response to a received mode selection signal, whether to perform a data check operation. The data check circuit is further configured to: perform data check on the stored data based on the first check code, and output the stored data obtained after the data check as first read data, when the mode selection signal indicates that the memory is in an on-die check mode; or directly output the stored data and the first check code as second read data when the mode selection signal indicates that the memory is in an off-die check mode.

A clock control circuit includes: a delay adjustment circuit, receiving a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal, and a determination result signal, and adjusting delays of the second phase clock signal, the third phase clock signal, and the fourth phase clock signal or adjust delays of the first phase clock signal, the second phase clock signal, and the fourth phase clock signal according to the determination result signal in a duty cycle adjustment training mode; and a determination circuit, recording a phase sequence of the first phase clock signal and the third phase clock signal at self-refresh exit timing, then comparing the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing.

Embodiments of this application provide a memory. The memory may include at least a first memory area, a peripheral circuit area, and a second memory area that are arranged in a first direction. The peripheral circuit area is located between the first memory area and the second memory area. The first memory area has a plurality of repeating units in a second direction. Each of the repeating units includes at least two memory banks arranged in the first direction. The first direction is perpendicular to the second direction.

The present disclosure provides an in-memory processing chip, which may include at least an interface circuit, a memory circuit, and a computing unit. A first transmission path exists between the interface circuit and the memory circuit; a second transmission path exists between the memory circuit and the computing unit; and a third transmission path exists between the interface circuit and the computing unit, and the third transmission path and the first transmission path are independent of each other.

A control circuit includes: a command decoding circuit, performing command decoding processing on a first pulse of a chip select signal and a command address signal based on a first clock signal to obtain a first command signal; an address decoding circuit, performing row address decoding processing on a second pulse of the chip select signal and the command address signal based on the first command signal and the first clock signal to obtain n second command signals; and a logic processing circuit, configured to perform logic processing based on the n second command signals to obtain n segment activation signals. A memory array includes m memory banks, each of the memory banks includes n segments, and both m and n are positive integers. Each of the segment activation signals is configured to indicate whether a segment corresponding to at least one of the m memory banks has been activated.

Provided are a control circuit, a control method, and a semiconductor memory. The control circuit includes a timing control module and a command control module. An output terminal of the timing control module is connected to an input terminal of the command control module. The timing control module is configured to receive a first clock signal, perform counting based on the first clock signal, generate an error check and scrub (ECS) flag signal, and send the ECS flag signal to the command control module. The ECS flag signal is in a valid state when a counting value meets a preset condition. The command control module is configured to receive the ECS flag signal, obtain a refresh command signal when the ECS flag signal is in the valid state, and generate an ECS command signal based on the refresh command signal.